commit e6eda804fa840f8ccb66a5af2188044e5c23731b
author Ahmed Ghazy <ax3ghazy@aucegypt.edu> Tue Oct 27 15:47:31 2020 +0200
committer Ahmed Ghazy <ax3ghazy@aucegypt.edu> Wed Oct 28 22:58:29 2020 +0200
tree 1682b55febc400571db2a63ccaf9f317a9023b26
parent 0b6219d234cc044a8fb7ed7b544b26631d207577

Fix a typo in a previous fix...

- IO_PADS -> PWR_PADS

verilog/rtl/mprj_ctrl.v

diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 9998814..60ca974 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -108,7 +108,7 @@
 `define LOAD	2'b11
 
     localparam IO_WORDS = (IO_PADS % 32 != 0) + (IO_PADS / 32);
-    localparam PWR_WORDS = (IO_PADS % 32 != 0) + (PWR_PADS / 32);
+    localparam PWR_WORDS = (PWR_PADS % 32 != 0) + (PWR_PADS / 32);
 
     localparam IO_BASE_ADR = (BASE_ADR | CONFIG) + ((IO_WORDS + PWR_WORDS - 2) * 4);
     localparam PWR_BASE_ADR = IO_BASE_ADR + (IO_PADS * 4);