Corrected the timer testbenches for minor count differences due to
the slightly different timing of the I/O configuration loading.

verilog/dv/caravel/mgmt_soc/timer/timer_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
index 9d04404..02fef69 100644
--- a/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer/timer_tb.v
@@ -69,8 +69,8 @@
 
 		/* Add checks here */
 		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7eb3)", countbits);
-		if(countbits !== 32'hdcba7eb3) begin
+		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
+		if(countbits !== 32'hdcba7cf3) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end
@@ -93,8 +93,8 @@
 		    $finish;
 		end
 		wait(checkbits == 6'h05);
-		$display("   countbits = %x (should be 0x117c)", countbits);
-		if(countbits !== 32'h117c) begin
+		$display("   countbits = %x (should be 0x12b4)", countbits);
+		if(countbits !== 32'h12b4) begin
 		    $display("Monitor: Test Timer (RTL) Failed");
 		    $finish;
 		end

verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v

diff --git a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
index b6db4b8..7de5463 100644
--- a/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
+++ b/verilog/dv/caravel/mgmt_soc/timer2/timer2_tb.v
@@ -69,8 +69,8 @@
 
 		/* Add checks here */
 		wait(checkbits == 6'h01);
-		$display("   countbits = 0x%x (should be 0xdcba7eb3)", countbits);
-		if(countbits !== 32'hdcba7eb3) begin
+		$display("   countbits = 0x%x (should be 0xdcba7cf3)", countbits);
+		if(countbits !== 32'hdcba7cf3) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
@@ -93,8 +93,8 @@
 		    $finish;
 		end
 		wait(checkbits == 6'h05);
-		$display("   countbits = %x (should be 0x117c)", countbits);
-		if(countbits !== 32'h117c) begin
+		$display("   countbits = %x (should be 0x12b4)", countbits);
+		if(countbits !== 32'h12b4) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end
@@ -114,8 +114,8 @@
 		end
 
 		wait(checkbits == 6'h08);
-		$display("   countbits = %x (should be 0x0219)", countbits);
-		if(countbits !== 32'h0219) begin
+		$display("   countbits = %x (should be 0x0259)", countbits);
+		if(countbits !== 32'h0259) begin
 		    $display("Monitor: Test Timer2 (RTL) Failed");
 		    $finish;
 		end