Various corrections to simplify the user project I/O wiring
connections into the management area. Corrected testbenches
for hkspi, mem, uart, perf, and gpio.
diff --git a/verilog/rtl/simple_spi_master.v b/verilog/rtl/simple_spi_master.v
index dad5471..a2a33b6 100755
--- a/verilog/rtl/simple_spi_master.v
+++ b/verilog/rtl/simple_spi_master.v
@@ -185,7 +185,7 @@
// No bidirectional 3-pin mode defined, so SDO is enabled whenever CSB is low.
assign sdoenb = icsb;
// assign sdo = (enable == 1'b0) ? 1'bz : icsb ? 1'bz : isdo;
- assign sdo = isdo;
+ assign sdo = (enable == 1'b0) ? 1'bz : isdo;
assign irq_out = irqena & done;
