commit c5265b80121a1cfca92cd2fdea7bdc375fb860bd
author Tim Edwards <tim@opencircuitdesign.com> Fri Sep 25 17:08:59 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Fri Sep 25 17:08:59 2020 -0400
tree d9521ddc48757c63709e36331f1574f2cdd23870
parent ef8312e0e966922a17c0d76b5a1e1f608703c6f3

Corrected some things from the initial pass of removing unused GPIO
signals and analog signals, and converting from EFS8A to sky130A.
Close to being able to simulate, with some hand-editing of the
standard cell library files.

verilog/rtl/ring_osc2x13.v

diff --git a/verilog/rtl/ring_osc2x13.v b/verilog/rtl/ring_osc2x13.v
index 4363c00..c0531bd 100644
--- a/verilog/rtl/ring_osc2x13.v
+++ b/verilog/rtl/ring_osc2x13.v
@@ -28,7 +28,7 @@
 
     sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(ts),
-	.TEB(trim[1]),
+	.TE_B(trim[1]),
 	.Z(d1)
     );
 
@@ -45,7 +45,7 @@
 
     sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(ts),
-	.TEB(trim[0]),
+	.TE_B(trim[0]),
 	.Z(out)
     );
 
@@ -72,7 +72,7 @@
 
     sky130_fd_sc_hd__einvn_4 delayenb1 (
 	.A(in),
-	.TEB(trim[1]),
+	.TE_B(trim[1]),
 	.Z(d1)
     );
 
@@ -89,7 +89,7 @@
 
     sky130_fd_sc_hd__einvn_8 delayenb0 (
 	.A(in),
-	.TEB(ctrl0),
+	.TE_B(ctrl0),
 	.Z(out)
     );