tree: 152a3121c2426f035ca40eaf6e6543a3e10bb81a [path history] [tgz]
  1. .travisCI/
  2. def/
  3. docs/
  4. gds/
  5. lef/
  6. macros/
  7. mag/
  8. maglef/
  9. ngspice/
  10. openlane/
  11. qflow/
  12. scripts/
  13. signoff/
  14. spi/
  15. utils/
  16. verilog/
  17. xschem/
  18. .travis.yml
  19. info.yaml
  22. Makefile
  23. Makefile.master
  24. manifest

PDK, Tools & Pre-requisites Installation

In order to get the caravel_fulgor_opamp project running several tools and files need to be installed. To simplify the installation and to make sure you fullfill all the pre-requisites an script is provided. To run the script just type on the console:


This script does the following:

General Purpose Open Source Operational Amplifier (OpAmp)

This project is a test chip, which contains several two stages operationals amplifiers with Miller compensation. This is an all analog desing implemented on the Google-Skywater 130nm Open Source PDK. It is an Open Source project underApache License 2.0.

The OpAmp desing is located in an Open Source SoC Harness obtained from the efabless Caravel Project.

Running the Tools


To run xschem and be able to simulate the OpAmp's test benches the following commands need to be run:

cd caravel_fulgor_opamp/xschem

In the xschem folder it is found the xschemrc file, where the paths to the xschem libraries are defined.


To run magic and be able to edit or desing a layout the following commands need to be run:

cd caravel_fulgor_opamp
magic -rcfile mag/dh.magicrc

The dh.magicrc file specifies where the open_pdk layout libraries are located. If magic is used without the -rcfile specification, the sky130 library won't be loaded.

OpAmp Desing

General Specifications:

  • V_{dd}
  • I_{ref}
  • Power Consumption
  • DC Gain
  • Bandwidth
  • Chip Area

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.