Revised the mprj_ctrl to treat the power control as a single bit
read/write per power domain, not part of the serial load chain.
This greatly simplifies the code in the mprj_ctrl module. Also
brought the power control pins up to the top level, in case we
want to use them for internally enabling/disabling the user area
power supplies (may be an experimental function on one or more
versions). Also: Corrected a few entries in the defs.h header
file, and added definitions for the bit fields in a number of
registers that have individual bitmask entries.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index f92fa36..478b9ee 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -83,6 +83,7 @@
// User Project pad data (when management SoC controls the pad)
input [MPRJ_IO_PADS-1:0] mgmt_in_data,
output [MPRJ_IO_PADS-1:0] mgmt_out_data,
+ output [MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
// IRQ
input irq_spi, // IRQ from standalone SPI
@@ -699,7 +700,8 @@
.sdo_oenb_state(sdo_oenb_state),
.jtag_oenb_state(jtag_oenb_state),
.mgmt_gpio_out(mgmt_out_pre),
- .mgmt_gpio_in(mgmt_in_data)
+ .mgmt_gpio_in(mgmt_in_data),
+ .pwr_ctrl_out(pwr_ctrl_out)
);
// Wishbone Slave RAM
