commit 856b092898d166106f28702cf979f7fa74cb3c47
author Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 16:30:22 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Fri Oct 09 16:30:22 2020 -0400
tree 9ba82f469af9e25375db6fe89a204bbe7243b4c5
parent b78e1c1b303373a41e7a4901008735070424a88e

Corrected the counter/timer and made an enhancement to respond to a
disable/enable sequence as a counter reset.  Generated testbenches
for both counter/timers.

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index f6cf0f6..e5375ff 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -153,14 +153,14 @@
     parameter FLASH_BASE_ADR  = 32'h 1000_0000;
     parameter UART_BASE_ADR   = 32'h 2000_0000;
     parameter GPIO_BASE_ADR   = 32'h 2100_0000;
-    parameter COUNTER_TIMER0_BASE_ADR = 32'h 2110_0000;
-    parameter COUNTER_TIMER1_BASE_ADR = 32'h 2120_0000;
-    parameter SPI_MASTER_BASE_ADR = 32'h 2130_0000;
-    parameter LA_BASE_ADR     = 32'h 2200_0000;
-    parameter MPRJ_CTRL_ADR   = 32'h 2300_0000;
-    parameter MPRJ_BASE_ADR   = 32'h 3000_0000;   // WB MI A
-    parameter SYS_BASE_ADR    = 32'h 2F00_0000;
+    parameter COUNTER_TIMER0_BASE_ADR = 32'h 2200_0000;
+    parameter COUNTER_TIMER1_BASE_ADR = 32'h 2300_0000;
+    parameter SPI_MASTER_BASE_ADR = 32'h 2400_0000;
+    parameter LA_BASE_ADR     = 32'h 2500_0000;
+    parameter MPRJ_CTRL_ADR   = 32'h 2600_0000;
     parameter FLASH_CTRL_CFG  = 32'h 2D00_0000;
+    parameter SYS_BASE_ADR    = 32'h 2F00_0000;
+    parameter MPRJ_BASE_ADR   = 32'h 3000_0000;   // WB MI A
     parameter XBAR_BASE_ADR   = 32'h 8000_0000;
 
     // UART