Added what can be pushed of chip_io
- Pad frame fully labelled on both sides
- This more like just the padframe, chip_io contains pad-to-pad
connections that is not done in this push
- Added its openlane config
diff --git a/openlane/Makefile b/openlane/Makefile
new file mode 100644
index 0000000..23fdf62
--- /dev/null
+++ b/openlane/Makefile
@@ -0,0 +1,35 @@
+BLOCKS = chip_io user_project_wrapper digital_pll mgmt_core
+CONFIG = $(foreach block,$(BLOCKS), ./$(block)/config.tcl)
+CLEAN = $(foreach block,$(BLOCKS), clean-$(block))
+
+all: $(BLOCKS)
+
+$(CONFIG) :
+ @echo "Missing $@. Please create a configuration for that design"
+ @exit 1
+
+$(BLOCKS) : % : ./%/config.tcl FORCE
+ifeq ($(OPENLANE_ROOT),)
+ @echo "Please export OPENLANE_ROOT"
+ @exit 1
+endif
+ @echo "###############################################"
+ @sleep 1
+ if [[ -f ./$*/interactive.tcl ]]; then\
+ ${OPENLANE_ROOT}/flow.tcl -it -file ./$*/interactive.tcl;\
+ else\
+ ${OPENLANE_ROOT}/flow.tcl -design ./$* -save_path .. -save -tag $* -overwrite;\
+ fi
+
+FORCE:
+
+clean:
+ @echo "Use clean_all to clean everything :)"
+
+clean_all: $(CLEAN)
+
+$(CLEAN): clean-% :
+ rm -rf runs/$*
+ rm -rf ../gds/$**
+ rm -rf ../mag/$**
+ rm -rf ../lef/$**
diff --git a/openlane/chip_io/config.tcl b/openlane/chip_io/config.tcl
new file mode 100644
index 0000000..7490488
--- /dev/null
+++ b/openlane/chip_io/config.tcl
@@ -0,0 +1,18 @@
+set script_dir [file dirname [file normalize [info script]]]
+
+set ::env(DESIGN_NAME) chip_io
+
+set ::env(VERILOG_FILES) "\
+ $script_dir/../../verilog/rtl/pads.v\
+ $script_dir/../../verilog/rtl/mprj_io.v\
+ $script_dir/../../verilog/rtl/chip_io.v"
+
+# The removal of this line is pending the IO verilog files being parsable by yosys...
+set ::env(VERILOG_FILES_BLACKBOX) "$script_dir/../../verilog/stubs/sky130_fd_io__top_xres4v2.v"
+
+set ::env(DESIGN_IS_PADFRAME) 1
+set ::env(SYNTH_FLAT_TOP) 1
+set ::env(USE_GPIO_PADS) 1
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 3200 5300"
diff --git a/openlane/chip_io/interactive.tcl b/openlane/chip_io/interactive.tcl
new file mode 100644
index 0000000..05ae7a1
--- /dev/null
+++ b/openlane/chip_io/interactive.tcl
@@ -0,0 +1,55 @@
+package require openlane
+set script_dir [file dirname [file normalize [info script]]]
+
+prep -design $script_dir -tag chip_io -overwrite
+set save_path $script_dir/../..
+
+verilog_elaborate
+
+init_floorplan
+
+exec -ignorestderr python3 $::env(SCRIPTS_DIR)/padringer.py\
+ --def-netlist $::env(CURRENT_DEF)\
+ --design $::env(DESIGN_NAME)\
+ --lefs $::env(TECH_LEF) {*}$::env(GPIO_PADS_LEF)\
+ -cfg $script_dir/padframe.cfg\
+ --working-dir $::env(TMP_DIR)\
+ -o $::env(RESULTS_DIR)/floorplan/padframe.def
+
+set_def $::env(RESULTS_DIR)/floorplan/padframe.def
+
+
+label_macro_pins\
+ -lef $::env(MERGED_LEF_UNPADDED)\
+ -netlist_def $::env(CURRENT_DEF)\
+ -pad_pin_name "PAD"\
+ -extra_args {-v\
+ --map mgmt_vdda_hvclamp_pad VDDA vdda INOUT\
+ --map user1_vdda_hvclamp_pad\\\[0\\] VDDA vdda1 INOUT\
+ --map user2_vdda_hvclamp_pad VDDA vdda2 INOUT\
+ --map mgmt_vssa_hvclamp_pad VSSA vssa INOUT\
+ --map user1_vssa_hvclamp_pad\\\[0\\] VSSA vssa1 INOUT\
+ --map user2_vssa_hvclamp_pad VSSA vssa2 INOUT\
+ --map mgmt_vccd_lvclamp_pad VCCD vccd INOUT\
+ --map user1_vccd_lvclamp_pad VCCD vccd1 INOUT\
+ --map user2_vccd_lvclamp_pad VCCD vccd2 INOUT\
+ --map mgmt_vssd_lvclmap_pad VSSD vssd INOUT\
+ --map user1_vssd_lvclmap_pad VSSD vssd1 INOUT\
+ --map user2_vssd_lvclmap_pad VSSD vssd2 INOUT\
+ --map mgmt_vddio_hvclamp_pad\\\[0\\] VDDIO vddio INOUT\
+ --map mgmt_vssio_hvclamp_pad\\\[0\\] VSSIO vssio INOUT}
+
+run_magic
+
+run_magic_drc
+
+save_views -lef_path $::env(magic_result_file_tag).lef \
+ -def_path $::env(CURRENT_DEF) \
+ -gds_path $::env(magic_result_file_tag).gds \
+ -mag_path $::env(magic_result_file_tag).mag \
+ -save_path $save_path \
+ -tag $::env(RUN_TAG)
+
+
+run_magic_spice_export
+run_lvs
diff --git a/openlane/chip_io/padframe.cfg b/openlane/chip_io/padframe.cfg
new file mode 100644
index 0000000..f37aec8
--- /dev/null
+++ b/openlane/chip_io/padframe.cfg
@@ -0,0 +1,73 @@
+AREA 3200 5300 ;
+
+CORNER mgmt_corner\[0\] SW sky130_ef_io__corner_pad ;
+CORNER mgmt_corner\[1\] NW sky130_ef_io__corner_pad ;
+CORNER user1_corner NE sky130_ef_io__corner_pad ;
+CORNER user2_corner SE sky130_ef_io__corner_pad ;
+
+PAD mprj_pads/area2_io_pad\[5\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[4\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[3\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[2\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[1\] N sky130_ef_io__gpiov2_pad ;
+PAD mgmt_vssio_hvclamp_pad\[0\] N sky130_ef_io__vssio_hvc_pad ;
+PAD mprj_pads/area2_io_pad\[0\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[17\] N sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[16\] N sky130_ef_io__gpiov2_pad ;
+PAD user1_vssa_hvclamp_pad\[0\] N sky130_ef_io__vssa_hvc_pad ;
+PAD mprj_pads/area1_io_pad\[15\] N sky130_ef_io__gpiov2_pad ;
+
+PAD mprj_pads/area1_io_pad\[0\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[1\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[2\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[3\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[4\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[5\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[6\] E sky130_ef_io__gpiov2_pad ;
+PAD user1_vssa_hvclamp_pad\[1\] E sky130_ef_io__vssa_hvc_pad ;
+PAD user1_vssd_lvclmap_pad E sky130_ef_io__vssd_lvc_pad ;
+PAD user1_vdda_hvclamp_pad\[1\] E sky130_ef_io__vdda_hvc_pad ;
+PAD mprj_pads/area1_io_pad\[7\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[8\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[9\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[10\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[11\] E sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area1_io_pad\[12\] E sky130_ef_io__gpiov2_pad ;
+PAD user1_vdda_hvclamp_pad\[0\] E sky130_ef_io__vdda_hvc_pad ;
+PAD mprj_pads/area1_io_pad\[13\] E sky130_ef_io__gpiov2_pad ;
+PAD user1_vccd_lvclamp_pad E sky130_ef_io__vccd_lvc_pad ;
+PAD mprj_pads/area1_io_pad\[14\] E sky130_ef_io__gpiov2_pad ;
+
+PAD mgmt_vssa_hvclamp_pad S sky130_ef_io__vssa_hvc_pad ;
+PAD resetb_pad S sky130_fd_io__top_xres4v2 ;
+PAD clock_pad S sky130_ef_io__gpiov2_pad ;
+PAD mgmt_vssd_lvclmap_pad S sky130_ef_io__vssd_lvc_pad ;
+PAD flash_csb_pad S sky130_ef_io__gpiov2_pad ;
+PAD flash_clk_pad S sky130_ef_io__gpiov2_pad ;
+PAD flash_io0_pad S sky130_ef_io__gpiov2_pad ;
+PAD flash_io1_pad S sky130_ef_io__gpiov2_pad ;
+PAD gpio_pad S sky130_ef_io__gpiov2_pad ;
+PAD mgmt_vssio_hvclamp_pad\[1\] S sky130_ef_io__vssio_hvc_pad ;
+PAD mgmt_vdda_hvclamp_pad S sky130_ef_io__vdda_hvc_pad ;
+
+PAD mgmt_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
+PAD mgmt_vddio_hvclamp_pad\[0\] W sky130_ef_io__vddio_hvc_pad ;
+PAD mprj_pads/area2_io_pad\[19\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[18\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[17\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[16\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[15\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[14\] W sky130_ef_io__gpiov2_pad ;
+PAD user2_vssd_lvclmap_pad W sky130_ef_io__vssd_lvc_pad ;
+PAD user2_vdda_hvclamp_pad W sky130_ef_io__vdda_hvc_pad ;
+PAD mprj_pads/area2_io_pad\[13\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[12\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[11\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[10\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[9\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[8\] W sky130_ef_io__gpiov2_pad ;
+PAD mprj_pads/area2_io_pad\[7\] W sky130_ef_io__gpiov2_pad ;
+PAD user2_vssa_hvclamp_pad W sky130_ef_io__vssa_hvc_pad ;
+PAD mgmt_vddio_hvclamp_pad\[1\] W sky130_ef_io__vddio_hvc_pad ;
+PAD user2_vccd_lvclamp_pad W sky130_ef_io__vccd_lvc_pad ;
+PAD mprj_pads/area2_io_pad\[6\] W sky130_ef_io__gpiov2_pad ;
