commit 6d9739daf9049ade53d95f23fe209ac73a31dab7
author Tim Edwards <tim@opencircuitdesign.com> Mon Oct 19 11:00:49 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Mon Oct 19 11:00:49 2020 -0400
tree 4e994b535b93712490ed7dd975da1c513bee5e4c
parent 60aeb5f8651cd88e3b7cb1b4982f6a992e6eef48

Removed references to "Mega-Project" and replaced them with "User Project".

verilog/rtl/chip_io.v

diff --git a/verilog/rtl/chip_io.v b/verilog/rtl/chip_io.v
index 9ea31ce..36b08df 100644
--- a/verilog/rtl/chip_io.v
+++ b/verilog/rtl/chip_io.v
@@ -48,7 +48,7 @@
 	output flash_io1_di_core,
 	// porbh, returned to the I/O level shifted down and inverted
 	input  por,
-	// Mega-project IOs
+	// User project IOs
 	inout [`MPRJ_IO_PADS-1:0] mprj_io,
 	input [`MPRJ_IO_PADS-1:0] mprj_io_out,
 	input [`MPRJ_IO_PADS-1:0] mprj_io_oeb,