| commit | 68e0363b0541a1cfd61500c8074b60480ea2cf5d | [log] [tgz] |
|---|---|---|
| author | Manar <manarabdelatty@aucegypt.edu> | Mon Nov 09 13:25:13 2020 +0200 |
| committer | Manar <manarabdelatty@aucegypt.edu> | Mon Nov 09 13:25:13 2020 +0200 |
| tree | 7cb2b164f76a7977b3ebd9e56cc448b2eebfc69d | |
| parent | 2517fa8538d616830340da4984502271fb902f19 [diff] [blame] |
Added power pins to the custom memory cells - connected mem_wb to power (guarded by lvs) - updated defines.v to use the custom memory
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v index cf0793d..d5fbd92 100644 --- a/verilog/rtl/mgmt_soc.v +++ b/verilog/rtl/mgmt_soc.v
@@ -740,6 +740,10 @@ wire [31:0] mem_dat_o; mem_wb soc_mem ( + `ifdef LVS + .VPWR(vdd1v8), + .VGND(vss), + `endif .wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i),