commit 61dce92ffadeb8742dadd290f03bc354f1405b8d
author Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:26:28 2020 +0200
committer Manar <manarabdelatty@aucegypt.edu> Tue Nov 10 19:32:02 2020 +0200
tree 8751c6a1c0dea69e4e7b2823bd62d5dfc10a3847
parent 9eeea83701d86ff4312d309c9250f1faadaf6d8e

Renamed lvs guard to use_power_pins

- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles

verilog/rtl/mgmt_soc.v

diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 4f26b40..df81c2c 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -44,7 +44,7 @@
 `include "convert_gpio_sigs.v"
 
 module mgmt_soc (
-`ifdef LVS
+`ifdef USE_POWER_PINS
     inout vdd1v8,	    /* 1.8V domain */
     inout vss,
 `endif
@@ -735,7 +735,7 @@
     wire [31:0] mem_dat_o;
 
     mem_wb soc_mem (
-    `ifdef LVS
+    `ifdef USE_POWER_PINS
         .VPWR(vdd1v8),
         .VGND(vss),
     `endif