Renamed lvs guard to use_power_pins
- Also, added guard to the cells in the custom memory
- dropped DLVS from the dv Makefiles
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 77cce42..06ceaf9 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -5,13 +5,13 @@
`include "ring_osc2x13.v"
module digital_pll(
-`ifdef LVS
+`ifdef USE_POWER_PINS
vdd,
vss,
`endif
resetb, enable, osc, clockp, div, dco, ext_trim);
-`ifdef LVS
+`ifdef USE_POWER_PINS
input vdd;
input vss;
`endif
