Ring Osc schem and spice
diff --git a/xschem/ring_vco/ring_osc.sch b/xschem/ring_vco/ring_osc.sch
new file mode 100644
index 0000000..ab7d719
--- /dev/null
+++ b/xschem/ring_vco/ring_osc.sch
@@ -0,0 +1,423 @@
+v { version=2.9.8 file_version=1.2}
+G {}
+K {}
+V {}
+S {}
+E {}
+N 0 30 -0 60 { lab=9}
+N 0 -60 -0 -30 { lab=10}
+N -80 0 -40 -0 { lab=out_ring}
+N 0 -80 0 -60 { lab=10}
+N 50 -0 70 0 { lab=o1}
+N 160 -0 180 -0 { lab=o2}
+N 270 -0 290 0 { lab=o3}
+N 380 -0 400 -0 { lab=o4}
+N 490 -0 510 0 { lab=o5}
+N 110 30 110 60 { lab=9}
+N 220 30 220 60 { lab=9}
+N 330 30 330 60 { lab=9}
+N 440 30 440 60 { lab=9}
+N 550 30 550 60 { lab=9}
+N 110 -80 110 -30 { lab=10}
+N 220 -80 220 -30 { lab=10}
+N 330 -80 330 -30 { lab=10}
+N 440 -80 440 -30 { lab=10}
+N 550 -80 550 -30 { lab=10}
+N 2640 0 2740 0 { lab=out_vco}
+N -0 -80 550 -80 { lab=10}
+N 550 -80 640 -80 { lab=10}
+N 290 -200 290 -80 { lab=10}
+N -160 -230 250 -230 { lab=5}
+N -200 -200 -200 150 { lab=5}
+N -160 180 250 180 { lab=in}
+N -200 -310 -200 -260 { lab=vdd}
+N -200 -310 290 -310 { lab=vdd}
+N 290 -310 290 -260 { lab=vdd}
+N 290 -230 360 -230 { lab=vdd}
+N 360 -310 360 -230 { lab=vdd}
+N 290 -310 360 -310 { lab=vdd}
+N -270 -230 -200 -230 { lab=vdd}
+N -270 -310 -270 -230 { lab=vdd}
+N -270 -310 -200 -310 { lab=vdd}
+N -200 210 -200 250 { lab=vss}
+N -200 250 290 250 { lab=vss}
+N 290 210 290 250 { lab=vss}
+N 290 180 370 180 { lab=vss}
+N 370 180 370 250 { lab=vss}
+N 290 250 370 250 { lab=vss}
+N -280 180 -200 180 { lab=vss}
+N -280 180 -280 250 { lab=vss}
+N -280 250 -200 250 { lab=vss}
+N -200 -140 -120 -140 { lab=5}
+N -120 -230 -120 -140 { lab=5}
+N 2480 -30 2480 30 { lab=out_ring}
+N 2480 0 2540 0 { lab=out_ring}
+N 2410 60 2440 60 { lab=#net1}
+N 2410 -60 2410 60 { lab=#net1}
+N 2410 -60 2440 -60 { lab=#net1}
+N 2480 -120 2480 -90 { lab=10}
+N 2410 -120 2480 -120 { lab=10}
+N 2410 -120 2410 -80 { lab=10}
+N 640 -80 690 -80 { lab=10}
+N 2480 90 2480 120 { lab=9}
+N 2410 120 2480 120 { lab=9}
+N 2410 80 2410 120 { lab=9}
+N 290 80 690 80 { lab=9}
+N 290 80 290 150 { lab=9}
+N 330 60 330 80 { lab=9}
+N 440 60 440 80 { lab=9}
+N 550 60 550 80 { lab=9}
+N -0 80 290 80 { lab=9}
+N -0 60 0 80 { lab=9}
+N 110 60 110 80 { lab=9}
+N 220 60 220 80 { lab=9}
+N 2640 -30 2640 30 { lab=out_vco}
+N 2640 90 2640 120 { lab=vss}
+N 2640 120 2730 120 { lab=vss}
+N 2730 60 2730 120 { lab=vss}
+N 2640 60 2730 60 { lab=vss}
+N 2570 60 2600 60 { lab=out_ring}
+N 2570 -60 2570 60 { lab=out_ring}
+N 2570 -60 2600 -60 { lab=out_ring}
+N 2540 0 2570 0 { lab=out_ring}
+N 2640 -120 2640 -90 { lab=vdd}
+N 2640 -120 2720 -120 { lab=vdd}
+N 2720 -120 2720 -60 { lab=vdd}
+N 2640 -60 2720 -60 { lab=vdd}
+N 2480 -60 2540 -60 { lab=10}
+N 2540 -120 2540 -60 { lab=10}
+N 2480 -120 2540 -120 { lab=10}
+N 2480 60 2560 60 { lab=vss}
+N 2560 60 2560 120 { lab=vss}
+N 600 -0 620 -0 { lab=o6}
+N 710 -0 730 -0 { lab=o7}
+N 690 80 910 80 { lab=9}
+N 690 -80 910 -80 { lab=10}
+N 660 -80 660 -30 { lab=10}
+N 770 -80 770 -30 { lab=10}
+N 770 30 770 80 { lab=9}
+N 660 30 660 80 { lab=9}
+N 910 80 1180 80 { lab=9}
+N 910 -80 1180 -80 { lab=10}
+N -60 10 -40 10 { lab=vss}
+N -60 10 -60 50 { lab=vss}
+N -60 50 720 50 { lab=vss}
+N 720 10 730 10 { lab=vss}
+N 720 10 720 50 { lab=vss}
+N 610 10 620 10 { lab=vss}
+N 610 10 610 50 { lab=vss}
+N 500 10 510 10 { lab=vss}
+N 500 10 500 50 { lab=vss}
+N 390 10 400 10 { lab=vss}
+N 390 10 390 50 { lab=vss}
+N 60 10 70 10 { lab=vss}
+N 60 10 60 50 { lab=vss}
+N 280 10 290 10 { lab=vss}
+N 280 10 280 50 { lab=vss}
+N 170 10 180 10 { lab=vss}
+N 170 10 170 50 { lab=vss}
+N 820 -0 840 -0 { lab=o8}
+N 930 -0 950 -0 { lab=#net2}
+N 1040 -0 1060 0 { lab=#net3}
+N 1150 -0 1180 -0 { lab=#net4}
+N 720 50 1160 50 { lab=vss}
+N 1160 10 1160 50 { lab=vss}
+N 1160 10 1180 10 { lab=vss}
+N 1050 10 1060 10 { lab=vss}
+N 1050 10 1050 50 { lab=vss}
+N 940 10 950 10 { lab=vss}
+N 940 10 940 50 { lab=vss}
+N 830 10 840 10 { lab=vss}
+N 830 10 830 50 { lab=vss}
+N 880 30 880 80 { lab=9}
+N 880 -80 880 -30 { lab=10}
+N 990 -80 990 -30 { lab=10}
+N 990 30 990 80 { lab=9}
+N 1100 30 1100 80 { lab=9}
+N 1100 -80 1100 -30 { lab=10}
+N 1220 30 1220 80 { lab=9}
+N 1180 80 1220 80 { lab=9}
+N 1220 -80 1220 -30 { lab=10}
+N 1180 -80 1220 -80 { lab=10}
+N 1220 80 1820 80 { lab=9}
+N 1220 -80 1820 -80 { lab=10}
+N 1340 30 1340 80 { lab=9}
+N 1340 -80 1340 -30 { lab=10}
+N 1460 30 1460 80 { lab=9}
+N 1460 -80 1460 -30 { lab=10}
+N 1580 -80 1580 -30 { lab=10}
+N 1580 30 1580 80 { lab=9}
+N 1160 50 1640 50 { lab=vss}
+N 1640 10 1640 50 { lab=vss}
+N 1640 10 1660 10 { lab=vss}
+N 1520 10 1540 10 { lab=vss}
+N 1520 10 1520 50 { lab=vss}
+N 1400 10 1420 10 { lab=vss}
+N 1400 10 1400 50 { lab=vss}
+N 1280 10 1300 10 { lab=vss}
+N 1280 10 1280 50 { lab=vss}
+N 1700 30 1700 80 { lab=9}
+N 1700 -80 1700 -30 { lab=10}
+N 1630 0 1660 0 { lab=#net5}
+N 1510 0 1540 0 { lab=#net6}
+N 1390 -0 1420 0 { lab=#net7}
+N 1270 0 1300 -0 { lab=#net8}
+N 1820 80 2030 80 { lab=9}
+N 1820 -80 2030 -80 { lab=10}
+N 1750 0 1780 -0 { lab=#net9}
+N 1640 50 1760 50 { lab=vss}
+N 1760 10 1760 50 { lab=vss}
+N 1760 10 1780 10 { lab=vss}
+N 1760 50 1880 50 { lab=vss}
+N 1880 10 1880 50 { lab=vss}
+N 1880 10 1910 10 { lab=vss}
+N 1820 30 1820 80 { lab=9}
+N 1950 30 1950 80 { lab=9}
+N 1950 -80 1950 -30 { lab=10}
+N 1820 -80 1820 -30 { lab=10}
+N 1870 -0 1910 -0 { lab=#net10}
+N 2010 10 2010 50 { lab=vss}
+N 2010 10 2030 10 { lab=vss}
+N 2000 0 2030 -0 { lab=#net11}
+N 1880 50 2010 50 { lab=vss}
+N 2030 80 2200 80 { lab=9}
+N 2030 -80 2200 -80 { lab=10}
+N 2070 -80 2070 -30 { lab=10}
+N 2070 30 2070 80 { lab=9}
+N 2280 80 2370 80 { lab=9}
+N 770 210 770 240 { lab=vdd}
+N 770 380 770 400 { lab=vss}
+N 670 310 700 310 { lab=out_vco}
+N 770 400 770 420 { lab=vss}
+N 640 310 670 310 { lab=out_vco}
+N 970 210 970 240 { lab=vdd}
+N 970 380 970 400 { lab=vss}
+N 870 310 900 310 { lab=outx2}
+N 970 400 970 420 { lab=vss}
+N 840 310 870 310 { lab=outx2}
+N 1170 210 1170 240 { lab=vdd}
+N 1170 380 1170 400 { lab=vss}
+N 1070 310 1100 310 { lab=outx4}
+N 1170 400 1170 420 { lab=vss}
+N 1040 310 1070 310 { lab=outx4}
+N 1370 210 1370 240 { lab=vdd}
+N 1370 380 1370 400 { lab=vss}
+N 1270 310 1300 310 { lab=outx8}
+N 1370 400 1370 420 { lab=vss}
+N 1240 310 1270 310 { lab=outx8}
+N 1570 210 1570 240 { lab=vdd}
+N 1570 380 1570 400 { lab=vss}
+N 1470 310 1500 310 { lab=outx16}
+N 1570 400 1570 420 { lab=vss}
+N 1440 310 1470 310 { lab=outx16}
+N 1640 310 1690 310 { lab=outx32}
+N 1760 310 1860 310 { lab=out}
+N 1760 280 1760 340 { lab=out}
+N 1760 400 1760 430 { lab=vss}
+N 1760 430 1850 430 { lab=vss}
+N 1850 370 1850 430 { lab=vss}
+N 1760 370 1850 370 { lab=vss}
+N 1690 370 1720 370 { lab=outx32}
+N 1690 250 1690 370 { lab=outx32}
+N 1690 250 1720 250 { lab=outx32}
+N 1760 190 1760 220 { lab=vdd}
+N 1760 190 1840 190 { lab=vdd}
+N 1840 190 1840 250 { lab=vdd}
+N 1760 250 1840 250 { lab=vdd}
+N 1860 310 1920 310 { lab=out}
+N 2370 80 2410 80 { lab=9}
+N 2200 80 2280 80 { lab=9}
+N 2200 -80 2290 -80 { lab=10}
+N 2290 -80 2410 -80 { lab=10}
+N 2350 0 2410 -0 { lab=#net1}
+N 2120 -0 2140 0 { lab=#net12}
+N 2150 20 2170 20 { lab=en}
+N 2220 70 2220 80 { lab=9}
+N 2120 70 2210 70 { lab=vss}
+N 2010 50 2120 50 { lab=vss}
+N 2120 50 2120 70 { lab=vss}
+N 2140 -20 2170 -20 { lab=#net12}
+N 2310 -0 2350 -0 { lab=#net1}
+N 2220 -80 2220 -70 { lab=10}
+N 2140 -20 2140 0 { lab=#net12}
+C {not.sym} 0 0 0 0 {name=x1}
+C {not.sym} 110 0 0 0 {name=x2}
+C {not.sym} 220 0 0 0 {name=x3}
+C {not.sym} 330 0 0 0 {name=x4}
+C {not.sym} 440 0 0 0 {name=x5}
+C {not.sym} 550 0 0 0 {name=x6}
+C {lab_pin.sym} -80 0 0 0 {name=l5 sig_type=std_logic lab=out_ring}
+C {lab_wire.sym} 2690 -120 0 0 {name=l11 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 2690 120 0 0 {name=l14 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 2460 60 0 0 {name=M1
+L=0.15
+W=1.2
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2460 -60 0 0 {name=M2
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 2620 60 0 0 {name=M3
+L=0.15
+W=0.6
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 2620 -60 0 0 {name=M4
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 2540 0 0 0 {name=l4 sig_type=std_logic lab=out_ring}
+C {lab_pin.sym} 2740 0 2 0 {name=l6 sig_type=std_logic lab=out_vco}
+C {sky130_fd_pr/pfet_01v8.sym} 270 -230 0 0 {name=M5
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} 270 180 0 0 {name=M6
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} -180 -230 0 1 {name=M7
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=pfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/nfet_01v8.sym} -180 180 0 1 {name=M8
+L=0.15
+W=0.9
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=1
+model=nfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 60 -230 0 0 {name=l7 sig_type=std_logic lab=5}
+C {lab_wire.sym} 60 -310 0 0 {name=l8 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 40 250 0 0 {name=l10 sig_type=std_logic lab=vss}
+C {lab_wire.sym} 40 180 0 0 {name=l12 sig_type=std_logic lab=in}
+C {lab_wire.sym} 290 -140 3 0 {name=l13 sig_type=std_logic lab=10}
+C {lab_wire.sym} 290 100 3 0 {name=l15 sig_type=std_logic lab=9}
+C {lab_wire.sym} 60 0 0 0 {name=l16 sig_type=std_logic lab=o1}
+C {lab_wire.sym} 170 0 0 0 {name=l17 sig_type=std_logic lab=o2}
+C {lab_wire.sym} 280 0 0 0 {name=l18 sig_type=std_logic lab=o3}
+C {lab_wire.sym} 390 0 0 0 {name=l19 sig_type=std_logic lab=o4}
+C {lab_wire.sym} 500 0 0 0 {name=l20 sig_type=std_logic lab=o5}
+C {lab_wire.sym} 610 0 0 0 {name=l21 sig_type=std_logic lab=o6}
+C {not.sym} 660 0 0 0 {name=x7}
+C {not.sym} 770 0 0 0 {name=x8}
+C {lab_wire.sym} 720 0 0 0 {name=l24 sig_type=std_logic lab=o7}
+C {lab_wire.sym} 830 0 0 0 {name=l25 sig_type=std_logic lab=o8}
+C {lab_wire.sym} -30 50 0 0 {name=l26 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 2560 120 3 0 {name=l27 sig_type=std_logic lab=vss}
+C {not.sym} 880 0 0 0 {name=x9}
+C {not.sym} 990 0 0 0 {name=x10}
+C {not.sym} 1100 0 0 0 {name=x11}
+C {not.sym} 1220 0 0 0 {name=x12}
+C {not.sym} 1340 0 0 0 {name=x13}
+C {not.sym} 1460 0 0 0 {name=x14}
+C {not.sym} 1580 0 0 0 {name=x15}
+C {not.sym} 1700 0 0 0 {name=x16}
+C {not.sym} 1820 0 0 0 {name=x17}
+C {not.sym} 1950 0 0 0 {name=x18}
+C {not.sym} 2070 0 0 0 {name=x19}
+C {FD_v2.sym} 770 310 0 0 {name=x21}
+C {lab_pin.sym} 770 210 1 0 {name=l28 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 770 420 3 0 {name=l29 sig_type=std_logic lab=vss}
+C {FD_v2.sym} 970 310 0 0 {name=x22}
+C {lab_pin.sym} 970 210 1 0 {name=l30 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 970 420 3 0 {name=l31 sig_type=std_logic lab=vss}
+C {FD_v2.sym} 1170 310 0 0 {name=x23}
+C {lab_pin.sym} 1170 210 1 0 {name=l32 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1170 420 3 0 {name=l33 sig_type=std_logic lab=vss}
+C {FD_v2.sym} 1370 310 0 0 {name=x24}
+C {lab_pin.sym} 1370 210 1 0 {name=l34 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1370 420 3 0 {name=l35 sig_type=std_logic lab=vss}
+C {FD_v2.sym} 1570 310 0 0 {name=x25}
+C {lab_pin.sym} 1570 210 1 0 {name=l36 sig_type=std_logic lab=vdd
+}
+C {lab_pin.sym} 1570 420 3 0 {name=l37 sig_type=std_logic lab=vss}
+C {lab_pin.sym} 640 310 0 0 {name=l38 sig_type=std_logic lab=out_vco}
+C {lab_pin.sym} 1920 310 2 0 {name=l39 sig_type=std_logic lab=out}
+C {lab_wire.sym} 1090 310 0 0 {name=l41 sig_type=std_logic lab=outx4}
+C {lab_wire.sym} 890 310 0 0 {name=l40 sig_type=std_logic lab=outx2}
+C {lab_wire.sym} 1290 310 0 0 {name=l42 sig_type=std_logic lab=outx8}
+C {lab_wire.sym} 1490 310 0 0 {name=l43 sig_type=std_logic lab=outx16}
+C {lab_wire.sym} 1810 190 0 0 {name=l45 sig_type=std_logic lab=vdd}
+C {lab_wire.sym} 1810 430 0 0 {name=l46 sig_type=std_logic lab=vss}
+C {sky130_fd_pr/nfet_01v8.sym} 1740 370 0 0 {name=M9
+L=0.15
+W=1.2
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=2
+model=nfet_01v8
+spiceprefix=X
+}
+C {sky130_fd_pr/pfet_01v8.sym} 1740 250 0 0 {name=M10
+L=0.15
+W=1.5
+ad="'W * 0.29'" pd="'2 * (W + 0.29)'"
+as="'W * 0.29'" ps="'2 * (W + 0.29)'"
+nrd="'0.29 / W'" nrs="'0.29 / W'"
+sa=0 sb=0 sd=0
+nf=1 mult=4
+model=pfet_01v8
+spiceprefix=X
+}
+C {lab_wire.sym} 1680 310 0 0 {name=l47 sig_type=std_logic lab=outx32}
+C {nand.sym} 2230 0 0 0 {name=x26}
+C {lab_pin.sym} 2150 20 0 0 {name=l51 sig_type=std_logic lab=en}
diff --git a/xschem/ring_vco/ring_osc.spice b/xschem/ring_vco/ring_osc.spice
new file mode 100644
index 0000000..0d9b7af
--- /dev/null
+++ b/xschem/ring_vco/ring_osc.spice
@@ -0,0 +1,117 @@
+**.subckt ring_osc
+x1 10 out_ring o1 9 vss not
+x2 10 o1 o2 9 vss not
+x3 10 o2 o3 9 vss not
+x4 10 o3 o4 9 vss not
+x5 10 o4 o5 9 vss not
+x6 10 o5 o6 9 vss not
+XM1 out_ring net1 9 vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM2 out_ring net1 10 10 sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2
+XM3 out_vco out_ring vss vss sky130_fd_pr__nfet_01v8 W=0.6 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM4 out_vco out_ring vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM5 10 5 vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM6 9 in vss vss sky130_fd_pr__nfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM7 5 5 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM8 5 in vss vss sky130_fd_pr__nfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+x7 10 o6 o7 9 vss not
+x8 10 o7 o8 9 vss not
+x9 10 o8 net2 9 vss not
+x10 10 net2 net3 9 vss not
+x11 10 net3 net4 9 vss not
+x12 10 net4 net8 9 vss not
+x13 10 net8 net7 9 vss not
+x14 10 net7 net6 9 vss not
+x15 10 net6 net5 9 vss not
+x16 10 net5 net9 9 vss not
+x17 10 net9 net10 9 vss not
+x18 10 net10 net11 9 vss not
+x19 10 net11 net12 9 vss not
+x21 out_vco vss outx2 vdd FD_v2
+x22 outx2 vss outx4 vdd FD_v2
+x23 outx4 vss outx8 vdd FD_v2
+x24 outx8 vss outx16 vdd FD_v2
+x25 outx16 vss outx32 vdd FD_v2
+XM9 out outx32 vss vss sky130_fd_pr__nfet_01v8 W=1.2 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=2 m=2
+XM10 out outx32 vdd vdd sky130_fd_pr__pfet_01v8 W=1.5 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=4 m=4
+x26 10 net12 net1 en 9 vss nand
+**.ends
+
+* expanding symbol: not.sym # of pins=5
+
+.subckt not vdd in out vss vbulk
+*.ipin vdd
+*.ipin in
+*.ipin vss
+*.opin out
+*.ipin vbulk
+XM1 out in vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM2 out in vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+.ends
+
+
+* expanding symbol: FD_v2.sym # of pins=4
+
+.subckt FD_v2 clk vss out vdd
+*.opin out
+*.ipin vdd
+*.ipin clk
+*.ipin vss
+XM1 1 4 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM2 1 4 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM3 1 clk 2 vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM4 1 clk_b 2 vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM5 3 2 vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM6 3 2 vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM7 3 clk_b out vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM8 3 clk out vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM9 4 out vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM10 4 out vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM11 clk_b clk vss vss sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM12 clk_b clk vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+.ends
+
+
+* expanding symbol: nand.sym # of pins=6
+
+.subckt nand vdd A OUT B vss vbulk
+*.opin OUT
+*.ipin vdd
+*.ipin A
+*.ipin B
+*.ipin vss
+*.ipin vbulk
+XM1 net1 B vss vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM2 OUT A net1 vbulk sky130_fd_pr__nfet_01v8 W=0.45 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM5 OUT A vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+XM6 OUT B vdd vdd sky130_fd_pr__pfet_01v8 W=0.9 L=0.15 ad='W * 0.29' pd='2 * (W + 0.29)' as='W * 0.29'
++ ps='2 * (W + 0.29)' nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 nf=1 mult=1 m=1
+.ends
+
+.end
