Add the custom DFF RAM
diff --git a/openlane/DFFRAM/config.tcl b/openlane/DFFRAM/config.tcl
new file mode 100644
index 0000000..7782cee
--- /dev/null
+++ b/openlane/DFFRAM/config.tcl
@@ -0,0 +1,25 @@
+set script_dir [file dirname [file normalize [info script]]]
+# User config
+set ::env(DESIGN_NAME) DFFRAM
+
+# Change if needed
+set ::env(VERILOG_FILES) $script_dir/../../verilog/gl/DFFRAM.gl.v
+set ::env(SYNTH_TOP_LEVEL) 1
+set ::env(SYNTH_READ_BLACKBOX_LIB) 1
+# Fill this
+set ::env(CLOCK_PERIOD) "10"
+set ::env(CLOCK_PORT) "CLK"
+set ::env(CLOCK_TREE_SYNTH) 0
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 630 630"
+
+set ::env(PDN_CFG) $script_dir/pdn.tcl
+
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
+set ::env(PL_TARGET_DENSITY) 0.85
+
+set ::env(CELL_PAD) 0
+set ::env(DIODE_INSERTION_STRATEGY) 0
diff --git a/openlane/DFFRAM/pdn.tcl b/openlane/DFFRAM/pdn.tcl
new file mode 100644
index 0000000..947bd06
--- /dev/null
+++ b/openlane/DFFRAM/pdn.tcl
@@ -0,0 +1,27 @@
+# Power nets
+set ::power_nets $::env(VDD_PIN)
+set ::ground_nets $::env(GND_PIN)
+
+
+pdngen::specify_grid stdcell {
+ name grid
+ rails {
+ met1 {width 0.48 pitch $::env(PLACE_SITE_HEIGHT) offset 0}
+ }
+ straps {
+ met4 {width 1.6 pitch $::env(FP_PDN_VPITCH) offset $::env(FP_PDN_VOFFSET)}
+ }
+ connect {{met1 met4}}
+}
+
+
+set ::halo 0
+
+# Metal layer for rails on every row
+set ::rails_mlayer "met1" ;
+
+# POWER or GROUND #Std. cell rails starting with power or ground rails at the bottom of the core area
+set ::rails_start_with "POWER" ;
+
+# POWER or GROUND #Upper metal stripes starting with power or ground rails at the left/bottom of the core area
+set ::stripes_start_with "POWER" ;
diff --git a/openlane/DFFRAM/pin_order.cfg b/openlane/DFFRAM/pin_order.cfg
new file mode 100644
index 0000000..297844f
--- /dev/null
+++ b/openlane/DFFRAM/pin_order.cfg
@@ -0,0 +1,12 @@
+#N
+Di.*
+
+#W
+A.*
+CLK
+WE.*
+EN
+
+
+#S
+Do.*
diff --git a/openlane/mgmt_core/config.tcl b/openlane/mgmt_core/config.tcl
index 51987a9..3f86edc 100644
--- a/openlane/mgmt_core/config.tcl
+++ b/openlane/mgmt_core/config.tcl
@@ -11,13 +11,13 @@
set ::env(FP_VERTICAL_HALO) 6
set ::env(FP_PIN_ORDER_CFG) $script_dir/pin_order.cfg
set ::env(FP_SIZING) absolute
-set ::env(DIE_AREA) "0 0 1800 1900"
+set ::env(DIE_AREA) "0 0 2600 1100"
set ::env(MACRO_PLACEMENT_CFG) $script_dir/macro_placement.cfg
set ::env(PL_TARGET_DENSITY) 0.37
-set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 0
-set ::env(CELL_PAD) 10
+set ::env(PL_OPENPHYSYN_OPTIMIZATIONS) 1
+set ::env(CELL_PAD) 8
set ::env(GLB_RT_ADJUSTMENT) 0
set ::env(GLB_RT_TILES) 14
@@ -34,10 +34,13 @@
$script_dir/../../verilog/rtl/housekeeping_spi.v"
set ::env(VERILOG_FILES_BLACKBOX) "\
+ $script_dir/../../verilog/gl/DFFRAM.gl.v
$script_dir/../../verilog/rtl/digital_pll.v"
set ::env(EXTRA_LEFS) "\
+ $script_dir/../../lef/DFFRAM.lef
$script_dir/../../lef/digital_pll.lef"
set ::env(EXTRA_GDS_FILES) "\
+ $script_dir/../../gds/DFFRAM.gds
$script_dir/../../gds/digital_pll.gds"
diff --git a/openlane/mgmt_core/macro_placement.cfg b/openlane/mgmt_core/macro_placement.cfg
index c81fd53..a1f7dde 100644
--- a/openlane/mgmt_core/macro_placement.cfg
+++ b/openlane/mgmt_core/macro_placement.cfg
@@ -1 +1,2 @@
-pll 15.225 1159.305 N
+pll 14.360 501.110 N
+soc.soc_mem.mem.SRAM 395.345 191.120 N
diff --git a/openlane/mgmt_core/pdn.tcl b/openlane/mgmt_core/pdn.tcl
index 5ed65a9..b74f931 100644
--- a/openlane/mgmt_core/pdn.tcl
+++ b/openlane/mgmt_core/pdn.tcl
@@ -17,7 +17,6 @@
}
pdngen::specify_grid macro {
- instance "pll"
power_pins "VPWR"
ground_pins "VGND"
blockages "li1 met1 met2 met3 met4"
