Revised the clocking scheme in several ways: (1) Removed the output
clock divider from the PLL to the clocking module; (2) changed the
clock divider from a power-of-2 divider to an integer-N divider;
(3) added an enable to the PLL separate from the bypass, so that the
PLL can be started and have time to settle before being switched in.
(4) Made some attempts at glitch-free clock switching when changing
to and from the PLL, and when changing output divider values.
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 5f1050d..91dfbd5 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -50,10 +50,6 @@
inout vdd1v8, /* 1.8V domain */
inout vss,
`endif
- input pll_clk,
- input ext_clk,
- input ext_clk_sel,
-
input clk,
input resetn,
@@ -319,7 +315,9 @@
irq[11] = irq_counter_timer1;
end
- // Assumption : no syscon module and wb_clk is the clock coming from the chip pin ?
+ // Assumption : no syscon module and wb_clk is the clock coming from the
+ // caravel_clocking module
+
assign wb_clk_i = clk;
assign wb_rst_i = ~resetn; // Redundant
