Revised the clocking scheme in several ways: (1) Removed the output
clock divider from the PLL to the clocking module; (2) changed the
clock divider from a power-of-2 divider to an integer-N divider;
(3) added an enable to the PLL separate from the bypass, so that the
PLL can be started and have time to settle before being switched in.
(4) Made some attempts at glitch-free clock switching when changing
to and from the PLL, and when changing output divider values.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 5fc90d4..79830be 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -41,12 +41,13 @@
`include "mgmt_soc.v"
`include "housekeeping_spi.v"
`include "digital_pll.v"
-`include "caravel_clkrst.v"
+`include "caravel_clocking.v"
`include "mgmt_core.v"
`include "mprj_io.v"
`include "chip_io.v"
`include "user_id_programming.v"
`include "gpio_control_block.v"
+`include "clock_div.v"
`include "simple_por.v"
/*------------------------------*/
@@ -339,7 +340,6 @@
.porb(porb_l),
// Clocks and reset
.clock(clock_core),
- .pll_clk16(pll_clk16),
.core_clk(caravel_clk),
.core_rstn(caravel_rstn),
// Logic Analyzer
