harness phase1 initial commit
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
new file mode 100644
index 0000000..5a3fba1
--- /dev/null
+++ b/verilog/dv/README.md
@@ -0,0 +1,13 @@
+# DV Tests
+
+Organized into two subdirectories:
+  * harness: contains tests for both the mangement SoC and the mega-project.
+  * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
+
+<pre>
+├── harness
+│   ├── mgmt_soc
+│   ├── mprj_counter
+└── wb_utests
+</pre>
+