commit 08cd6eba30b5b59bbd33a808a9173203d7a7175b
author Matt Venn <matt@mattvenn.net> Mon Nov 16 12:01:14 2020 +0100
committer Matt Venn <matt@mattvenn.net> Mon Nov 16 12:01:14 2020 +0100
tree ed5d102ae14d7dca40e78ce0ae9a81ec0548cfd8
parent d4cc669e6b40d8f170c2674fe18ae0f43093f0c3

add default nettype none

verilog/rtl/digital_pll.v

diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 06ceaf9..dac708a 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // Digital PLL (ring oscillator + controller)
 // Technically this is a frequency locked loop, not a phase locked loop.