Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example"
and made the filename equal to the module name, for clarity.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index a39fdea..3e92b15 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -41,7 +41,6 @@
`include "housekeeping_spi.v"
`include "digital_pll.v"
`include "caravel_clkrst.v"
-`include "mprj_counter.v"
`include "mgmt_core.v"
`include "mprj_io.v"
`include "chip_io.v"
@@ -49,6 +48,11 @@
`include "gpio_control_block.v"
`include "simple_por.v"
+/*------------------------------*/
+/* Include user project here */
+/*------------------------------*/
+`include "user_proj_example.v"
+
`ifdef USE_OPENRAM
`include "sram_1rw1r_32_8192_8_sky130.v"
`endif
@@ -352,7 +356,11 @@
.TE_B(la_oen)
);
- mega_project mprj (
+ /*--------------------------------------*/
+ /* User project is instantiated here */
+ /*--------------------------------------*/
+
+ user_proj_example mprj (
.wb_clk_i(caravel_clk),
.wb_rst_i(!caravel_rstn),
// MGMT SoC Wishbone Slave
@@ -369,10 +377,14 @@
.la_data_out(la_data_out_mprj),
.la_oen (la_oen),
// IO Pads
- .io_in (mprj_io_in),
- .io_out() // ???
+ .io_in (user_io_in),
+ .io_out(user_io_out)
);
+ /*--------------------------------------*/
+ /* End user project instantiation */
+ /*--------------------------------------*/
+
wire [`MPRJ_IO_PADS-1:0] gpio_serial_link_shifted;
assign gpio_serial_link_shifted = {gpio_serial_link[`MPRJ_IO_PADS-2:0], mprj_io_loader_data};
