Most testbenches are working again now. Renamed "mprj_counter" to "user_proj_example"
and made the filename equal to the module name, for clarity.
diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 5a3fba1..2f4a77d 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -1,13 +1,13 @@
# DV Tests
Organized into two subdirectories:
- * harness: contains tests for both the mangement SoC and the mega-project.
+ * caravel: contains tests for both the mangement SoC and an example user project.
* wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
<pre>
├── harness
│ ├── mgmt_soc
-│ ├── mprj_counter
+│ ├── user_proj_example
└── wb_utests
</pre>
