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shalanfd13eb52020-08-21 16:48:07 +02001/*
2 * PicoSoC - A simple example SoC using PicoRV32
3 *
4 * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * Revision 1, July 2019: Added signals to drive flash_clk and flash_csb
19 * output enable (inverted), tied to reset so that the flash is completely
20 * isolated from the processor when the processor is in reset.
21 *
22 * Also: Made ram_wenb a 4-bit bus so that the memory access can be made
23 * byte-wide for byte-wide instructions.
24 */
25
26`ifdef PICORV32_V
Tim Edwards04ba17f2020-10-02 22:27:50 -040027`error "mgmt_soc.v must be read before picorv32.v!"
shalanfd13eb52020-08-21 16:48:07 +020028`endif
29
Tim Edwards04ba17f2020-10-02 22:27:50 -040030`define PICORV32_REGS mgmt_soc_regs
shalanfd13eb52020-08-21 16:48:07 +020031
32`include "picorv32.v"
33`include "spimemio.v"
34`include "simpleuart.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040035`include "simple_spi_master.v"
Tim Edwards7be29a22020-10-25 21:50:19 -040036`include "counter_timer_high.v"
37`include "counter_timer_low.v"
shalanfd13eb52020-08-21 16:48:07 +020038`include "wb_intercon.v"
39`include "mem_wb.v"
40`include "gpio_wb.v"
shalanfd13eb52020-08-21 16:48:07 +020041`include "sysctrl.v"
42`include "la_wb.v"
shalan0d14e6e2020-08-31 16:50:48 +020043`include "mprj_ctrl.v"
Tim Edwards04ba17f2020-10-02 22:27:50 -040044`include "convert_gpio_sigs.v"
Manar14d35ac2020-10-21 22:47:15 +020045`include "mem_synth_wb.v"
shalanfd13eb52020-08-21 16:48:07 +020046
Tim Edwards9eda80d2020-10-08 21:36:44 -040047module mgmt_soc #(
48 parameter MPRJ_IO_PADS = 32,
49 parameter MPRJ_PWR_PADS = 32
50) (
shalanfd13eb52020-08-21 16:48:07 +020051`ifdef LVS
52 inout vdd1v8, /* 1.8V domain */
53 inout vss,
54`endif
shalanfd13eb52020-08-21 16:48:07 +020055 input clk,
56 input resetn,
57
Tim Edwards04ba17f2020-10-02 22:27:50 -040058 // Trap state from CPU
59 output trap,
60
61 // GPIO (one pin)
62 output gpio_out_pad, // Connect to out on gpio pad
63 input gpio_in_pad, // Connect to in on gpio pad
64 output gpio_mode0_pad, // Connect to dm[0] on gpio pad
65 output gpio_mode1_pad, // Connect to dm[2] on gpio pad
66 output gpio_outenb_pad, // Connect to oe_n on gpio pad
67 output gpio_inenb_pad, // Connect to inp_dis on gpio pad
shalanfd13eb52020-08-21 16:48:07 +020068
69 // LA signals
Tim Edwards6d9739d2020-10-19 11:00:49 -040070 input [127:0] la_input, // From User Project to cpu
71 output [127:0] la_output, // From CPU to User Project
shalan0d14e6e2020-08-31 16:50:48 +020072 output [127:0] la_oen, // LA output enable (active low)
73
Tim Edwards6d9739d2020-10-19 11:00:49 -040074 // User Project I/O Configuration (serial load)
Tim Edwards05ad4fc2020-10-19 22:12:33 -040075 input mprj_vcc_pwrgood,
76 input mprj2_vcc_pwrgood,
77 input mprj_vdd_pwrgood,
78 input mprj2_vdd_pwrgood,
Tim Edwards04ba17f2020-10-02 22:27:50 -040079 output mprj_io_loader_resetn,
80 output mprj_io_loader_clock,
81 output mprj_io_loader_data,
shalanfd13eb52020-08-21 16:48:07 +020082
Tim Edwards6d9739d2020-10-19 11:00:49 -040083 // User Project pad data (when management SoC controls the pad)
Tim Edwards44bab472020-10-04 22:09:54 -040084 input [MPRJ_IO_PADS-1:0] mgmt_in_data,
85 output [MPRJ_IO_PADS-1:0] mgmt_out_data,
shalanfd13eb52020-08-21 16:48:07 +020086
87 // IRQ
shalanfd13eb52020-08-21 16:48:07 +020088 input irq_spi, // IRQ from standalone SPI
89
shalanfd13eb52020-08-21 16:48:07 +020090 // Flash memory control (SPI master)
91 output flash_csb,
92 output flash_clk,
93
94 output flash_csb_oeb,
95 output flash_clk_oeb,
96
97 output flash_io0_oeb,
98 output flash_io1_oeb,
99 output flash_io2_oeb,
100 output flash_io3_oeb,
101
102 output flash_csb_ieb,
103 output flash_clk_ieb,
104
105 output flash_io0_ieb,
106 output flash_io1_ieb,
107 output flash_io2_ieb,
108 output flash_io3_ieb,
109
110 output flash_io0_do,
111 output flash_io1_do,
112 output flash_io2_do,
113 output flash_io3_do,
114
115 input flash_io0_di,
116 input flash_io1_di,
117 input flash_io2_di,
118 input flash_io3_di,
119
Tim Edwards04ba17f2020-10-02 22:27:50 -0400120 // SPI pass-thru mode
121 input pass_thru_mgmt,
122 input pass_thru_mgmt_csb,
123 input pass_thru_mgmt_sck,
124 input pass_thru_mgmt_sdi,
125 output pass_thru_mgmt_sdo,
126
Tim Edwards81153202020-10-09 19:57:04 -0400127 // SPI master->slave direct link
128 output hk_connect,
Tim Edwards32d05422020-10-19 19:43:52 -0400129 // User clock monitoring
130 input user_clk,
Tim Edwards81153202020-10-09 19:57:04 -0400131
Tim Edwards6d9739d2020-10-19 11:00:49 -0400132 // WB MI A (User project)
shalan0d14e6e2020-08-31 16:50:48 +0200133 input mprj_ack_i,
Tim Edwardsef8312e2020-09-22 17:20:06 -0400134 input [31:0] mprj_dat_i,
shalan0d14e6e2020-08-31 16:50:48 +0200135 output mprj_cyc_o,
Tim Edwardsef8312e2020-09-22 17:20:06 -0400136 output mprj_stb_o,
137 output mprj_we_o,
138 output [3:0] mprj_sel_o,
139 output [31:0] mprj_adr_o,
Manar98a7adc2020-10-19 23:21:36 +0200140 output [31:0] mprj_dat_o
shalanfd13eb52020-08-21 16:48:07 +0200141);
142 /* Memory reverted back to 256 words while memory has to be synthesized */
Manar14d35ac2020-10-21 22:47:15 +0200143 parameter integer MEM_WORDS = 256;
144 parameter integer MEM_SYNTH_WORDS = 1024;
145 parameter [31:0] STACKADDR = (4*(MEM_WORDS + MEM_SYNTH_WORDS)); // end of memory
shalanfd13eb52020-08-21 16:48:07 +0200146 parameter [31:0] PROGADDR_RESET = 32'h 1000_0000;
147 parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
148
149 // Slaves Base Addresses
Tim Edwards04ba17f2020-10-02 22:27:50 -0400150 parameter RAM_BASE_ADR = 32'h 0000_0000;
Manar14d35ac2020-10-21 22:47:15 +0200151 parameter RAM_SYNTH_BASE_ADR = 32'h 0100_0000;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400152 parameter FLASH_BASE_ADR = 32'h 1000_0000;
153 parameter UART_BASE_ADR = 32'h 2000_0000;
154 parameter GPIO_BASE_ADR = 32'h 2100_0000;
Tim Edwards856b0922020-10-09 16:30:22 -0400155 parameter COUNTER_TIMER0_BASE_ADR = 32'h 2200_0000;
156 parameter COUNTER_TIMER1_BASE_ADR = 32'h 2300_0000;
157 parameter SPI_MASTER_BASE_ADR = 32'h 2400_0000;
158 parameter LA_BASE_ADR = 32'h 2500_0000;
159 parameter MPRJ_CTRL_ADR = 32'h 2600_0000;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400160 parameter FLASH_CTRL_CFG = 32'h 2D00_0000;
Tim Edwards856b0922020-10-09 16:30:22 -0400161 parameter SYS_BASE_ADR = 32'h 2F00_0000;
162 parameter MPRJ_BASE_ADR = 32'h 3000_0000; // WB MI A
shalanfd13eb52020-08-21 16:48:07 +0200163
164 // UART
165 parameter UART_CLK_DIV = 8'h00;
166 parameter UART_DATA = 8'h04;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400167
168 // SPI Master
169 parameter SPI_MASTER_CONFIG = 8'h00;
170 parameter SPI_MASTER_DATA = 8'h04;
171
172 // Counter-timer 0
173 parameter COUNTER_TIMER0_CONFIG = 8'h00;
174 parameter COUNTER_TIMER0_VALUE = 8'h04;
175 parameter COUNTER_TIMER0_DATA = 8'h08;
176
177 // Counter-timer 1
178 parameter COUNTER_TIMER1_CONFIG = 8'h00;
179 parameter COUNTER_TIMER1_VALUE = 8'h04;
180 parameter COUNTER_TIMER1_DATA = 8'h08;
shalanfd13eb52020-08-21 16:48:07 +0200181
182 // SOC GPIO
183 parameter GPIO_DATA = 8'h00;
184 parameter GPIO_ENA = 8'h04;
185 parameter GPIO_PU = 8'h08;
186 parameter GPIO_PD = 8'h0c;
187
shalan0d14e6e2020-08-31 16:50:48 +0200188 // LA
shalanfd13eb52020-08-21 16:48:07 +0200189 parameter LA_DATA_0 = 8'h00;
190 parameter LA_DATA_1 = 8'h04;
191 parameter LA_DATA_2 = 8'h08;
192 parameter LA_DATA_3 = 8'h0c;
193 parameter LA_ENA_0 = 8'h10;
194 parameter LA_ENA_1 = 8'h14;
195 parameter LA_ENA_2 = 8'h18;
196 parameter LA_ENA_3 = 8'h1c;
197
shalanfd13eb52020-08-21 16:48:07 +0200198 // System Control Registers
Tim Edwards32d05422020-10-19 19:43:52 -0400199 parameter PWRGOOD = 8'h00;
200 parameter CLK_OUT = 8'h04;
201 parameter TRAP_OUT = 8'h08;
202 parameter IRQ_SRC = 8'h0c;
shalanfd13eb52020-08-21 16:48:07 +0200203
204 // Wishbone Interconnect
205 localparam ADR_WIDTH = 32;
206 localparam DAT_WIDTH = 32;
Manar14d35ac2020-10-21 22:47:15 +0200207 localparam NUM_SLAVES = 13;
shalanfd13eb52020-08-21 16:48:07 +0200208
209 parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
shalanfd13eb52020-08-21 16:48:07 +0200210 {8'hFF, {ADR_WIDTH-8{1'b0}}},
211 {8'hFF, {ADR_WIDTH-8{1'b0}}},
212 {8'hFF, {ADR_WIDTH-8{1'b0}}},
213 {8'hFF, {ADR_WIDTH-8{1'b0}}},
214 {8'hFF, {ADR_WIDTH-8{1'b0}}},
215 {8'hFF, {ADR_WIDTH-8{1'b0}}},
216 {8'hFF, {ADR_WIDTH-8{1'b0}}},
shalan0d14e6e2020-08-31 16:50:48 +0200217 {8'hFF, {ADR_WIDTH-8{1'b0}}},
218 {8'hFF, {ADR_WIDTH-8{1'b0}}},
Tim Edwards04ba17f2020-10-02 22:27:50 -0400219 {8'hFF, {ADR_WIDTH-8{1'b0}}},
220 {8'hFF, {ADR_WIDTH-8{1'b0}}},
Manar14d35ac2020-10-21 22:47:15 +0200221 {8'hFF, {ADR_WIDTH-8{1'b0}}},
shalanfd13eb52020-08-21 16:48:07 +0200222 {8'hFF, {ADR_WIDTH-8{1'b0}}}
223 };
shalan0d14e6e2020-08-31 16:50:48 +0200224
shalanfd13eb52020-08-21 16:48:07 +0200225 parameter [NUM_SLAVES*ADR_WIDTH-1: 0] SLAVE_ADR = {
shalanfd13eb52020-08-21 16:48:07 +0200226 {SYS_BASE_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200227 {FLASH_CTRL_CFG},
shalan0d14e6e2020-08-31 16:50:48 +0200228 {MPRJ_BASE_ADR},
229 {MPRJ_CTRL_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200230 {LA_BASE_ADR},
Tim Edwards04ba17f2020-10-02 22:27:50 -0400231 {SPI_MASTER_BASE_ADR},
232 {COUNTER_TIMER1_BASE_ADR},
233 {COUNTER_TIMER0_BASE_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200234 {GPIO_BASE_ADR},
235 {UART_BASE_ADR},
236 {FLASH_BASE_ADR},
Manar14d35ac2020-10-21 22:47:15 +0200237 {RAM_SYNTH_BASE_ADR},
shalanfd13eb52020-08-21 16:48:07 +0200238 {RAM_BASE_ADR}
239 };
240
Tim Edwardsca2f3182020-10-06 10:05:11 -0400241 // The following functions are connected to specific user project
242 // area pins, when under control of the management area (during
243 // startup, and when not otherwise programmed for the user project).
244
245 // JTAG = jtag_out (inout)
246 // SDO = sdo_out (output) (shared with SPI master)
247 // SDI = mgmt_in_data[2] (input) (shared with SPI master)
248 // CSB = mgmt_in_data[3] (input) (shared with SPI master)
249 // SCK = mgmt_in_data[4] (input) (shared with SPI master)
250 // ser_rx = mgmt_in_data[5] (input)
251 // ser_tx = mgmt_out_data[6] (output)
252 // irq_pin = mgmt_in_data[7] (input)
253 // flash_csb = mgmt_out_data[8] (output) (user area flash)
254 // flash_sck = mgmt_out_data[9] (output) (user area flash)
255 // flash_io0 = mgmt_in/out_data[10] (input) (user area flash)
256 // flash_io1 = mgmt_in/out_data[11] (output) (user area flash)
Tim Edwards32d05422020-10-19 19:43:52 -0400257 // irq2_pin = mgmt_in_data[12] (input)
258 // trap_mon = mgmt_in_data[13] (output)
259 // clk1_mon = mgmt_in_data[14] (output)
260 // clk2_mon = mgmt_in_data[15] (output)
Tim Edwardsca2f3182020-10-06 10:05:11 -0400261
262 // OEB lines for [0] and [1] are the only ones connected directly to
263 // the pad. All others have OEB controlled by the configuration bit
264 // in the control block.
265
shalanfd13eb52020-08-21 16:48:07 +0200266 // memory-mapped I/O control registers
Tim Edwards04ba17f2020-10-02 22:27:50 -0400267 wire gpio_pullup; // Intermediate GPIO pullup
268 wire gpio_pulldown; // Intermediate GPIO pulldown
269 wire gpio_outenb; // Intermediate GPIO out enable (bar)
270 wire gpio_out; // Intermediate GPIO output
shalanfd13eb52020-08-21 16:48:07 +0200271
Tim Edwardsef8312e2020-09-22 17:20:06 -0400272 wire trap_output_dest; // Trap signal output destination
Tim Edwards32d05422020-10-19 19:43:52 -0400273 wire clk1_output_dest; // Core clock1 signal output destination
274 wire clk2_output_dest; // Core clock2 signal output destination
Tim Edwardsef8312e2020-09-22 17:20:06 -0400275 wire irq_7_inputsrc; // IRQ 7 source
Tim Edwards32d05422020-10-19 19:43:52 -0400276 wire irq_8_inputsrc; // IRQ 8 source
shalanfd13eb52020-08-21 16:48:07 +0200277
Tim Edwardsef8312e2020-09-22 17:20:06 -0400278 // Convert GPIO signals to sky130_fd_io pad signals
Tim Edwards04ba17f2020-10-02 22:27:50 -0400279 convert_gpio_sigs convert_gpio_bit (
shalanfd13eb52020-08-21 16:48:07 +0200280 .gpio_out(gpio_out),
281 .gpio_outenb(gpio_outenb),
282 .gpio_pu(gpio_pullup),
283 .gpio_pd(gpio_pulldown),
284 .gpio_out_pad(gpio_out_pad),
285 .gpio_outenb_pad(gpio_outenb_pad),
286 .gpio_inenb_pad(gpio_inenb_pad),
287 .gpio_mode1_pad(gpio_mode1_pad),
288 .gpio_mode0_pad(gpio_mode0_pad)
289 );
290
291 reg [31:0] irq;
292 wire irq_7;
Tim Edwards32d05422020-10-19 19:43:52 -0400293 wire irq_8;
shalanfd13eb52020-08-21 16:48:07 +0200294 wire irq_stall;
295 wire irq_uart;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400296 wire irq_spi_master;
297 wire irq_counter_timer0;
298 wire irq_counter_timer1;
shalanfd13eb52020-08-21 16:48:07 +0200299
shalanfd13eb52020-08-21 16:48:07 +0200300 assign irq_stall = 0;
Tim Edwardsca2f3182020-10-06 10:05:11 -0400301 assign irq_7 = (irq_7_inputsrc == 1'b1) ? mgmt_in_data[7] : 1'b0;
Tim Edwards32d05422020-10-19 19:43:52 -0400302 assign irq_8 = (irq_8_inputsrc == 1'b1) ? mgmt_in_data[12] : 1'b0;
shalanfd13eb52020-08-21 16:48:07 +0200303
304 always @* begin
305 irq = 0;
306 irq[3] = irq_stall;
307 irq[4] = irq_uart;
shalanfd13eb52020-08-21 16:48:07 +0200308 irq[6] = irq_spi;
309 irq[7] = irq_7;
Tim Edwards04ba17f2020-10-02 22:27:50 -0400310 irq[9] = irq_spi_master;
311 irq[10] = irq_counter_timer0;
312 irq[11] = irq_counter_timer1;
shalanfd13eb52020-08-21 16:48:07 +0200313 end
314
Tim Edwards3245e2f2020-10-10 14:02:11 -0400315 // Assumption : no syscon module and wb_clk is the clock coming from the
316 // caravel_clocking module
317
shalanfd13eb52020-08-21 16:48:07 +0200318 assign wb_clk_i = clk;
319 assign wb_rst_i = ~resetn; // Redundant
320
321 // Wishbone Master
322 wire [31:0] cpu_adr_o;
323 wire [31:0] cpu_dat_i;
324 wire [3:0] cpu_sel_o;
325 wire cpu_we_o;
326 wire cpu_cyc_o;
327 wire cpu_stb_o;
328 wire [31:0] cpu_dat_o;
329 wire cpu_ack_i;
shalanfd13eb52020-08-21 16:48:07 +0200330
331 picorv32_wb #(
332 .STACKADDR(STACKADDR),
333 .PROGADDR_RESET(PROGADDR_RESET),
334 .PROGADDR_IRQ(PROGADDR_IRQ),
335 .BARREL_SHIFTER(1),
336 .COMPRESSED_ISA(1),
337 .ENABLE_MUL(1),
338 .ENABLE_DIV(1),
339 .ENABLE_IRQ(1),
340 .ENABLE_IRQ_QREGS(0)
341 ) cpu (
342 .wb_clk_i (wb_clk_i),
343 .wb_rst_i (wb_rst_i),
344 .trap (trap),
345 .irq (irq),
346 .mem_instr(mem_instr),
347 .wbm_adr_o(cpu_adr_o),
348 .wbm_dat_i(cpu_dat_i),
349 .wbm_stb_o(cpu_stb_o),
350 .wbm_ack_i(cpu_ack_i),
351 .wbm_cyc_o(cpu_cyc_o),
352 .wbm_dat_o(cpu_dat_o),
353 .wbm_we_o(cpu_we_o),
354 .wbm_sel_o(cpu_sel_o)
355 );
356
357 // Wishbone Slave SPIMEMIO
358 wire spimemio_flash_stb_i;
359 wire spimemio_flash_ack_o;
360 wire [31:0] spimemio_flash_dat_o;
361
362 wire spimemio_cfg_stb_i;
363 wire spimemio_cfg_ack_o;
364 wire [31:0] spimemio_cfg_dat_o;
365
366 spimemio_wb spimemio (
367 .wb_clk_i(wb_clk_i),
368 .wb_rst_i(wb_rst_i),
369
370 .wb_adr_i(cpu_adr_o),
371 .wb_dat_i(cpu_dat_o),
372 .wb_sel_i(cpu_sel_o),
373 .wb_we_i(cpu_we_o),
374 .wb_cyc_i(cpu_cyc_o),
375
376 // FLash Slave
377 .wb_flash_stb_i(spimemio_flash_stb_i),
378 .wb_flash_ack_o(spimemio_flash_ack_o),
379 .wb_flash_dat_o(spimemio_flash_dat_o),
380
381 // Config Register Slave
382 .wb_cfg_stb_i(spimemio_cfg_stb_i),
383 .wb_cfg_ack_o(spimemio_cfg_ack_o),
384 .wb_cfg_dat_o(spimemio_cfg_dat_o),
385
Tim Edwards04ba17f2020-10-02 22:27:50 -0400386 .pass_thru(pass_thru_mgmt),
387 .pass_thru_csb(pass_thru_mgmt_csb),
388 .pass_thru_sck(pass_thru_mgmt_sck),
389 .pass_thru_sdi(pass_thru_mgmt_sdi),
390 .pass_thru_sdo(pass_thru_mgmt_sdo),
391
shalanfd13eb52020-08-21 16:48:07 +0200392 .flash_csb (flash_csb),
393 .flash_clk (flash_clk),
394
395 .flash_csb_oeb (flash_csb_oeb),
396 .flash_clk_oeb (flash_clk_oeb),
397
398 .flash_io0_oeb (flash_io0_oeb),
399 .flash_io1_oeb (flash_io1_oeb),
400 .flash_io2_oeb (flash_io2_oeb),
401 .flash_io3_oeb (flash_io3_oeb),
402
403 .flash_csb_ieb (flash_csb_ieb),
404 .flash_clk_ieb (flash_clk_ieb),
405
406 .flash_io0_ieb (flash_io0_ieb),
407 .flash_io1_ieb (flash_io1_ieb),
408 .flash_io2_ieb (flash_io2_ieb),
409 .flash_io3_ieb (flash_io3_ieb),
410
411 .flash_io0_do (flash_io0_do),
412 .flash_io1_do (flash_io1_do),
413 .flash_io2_do (flash_io2_do),
414 .flash_io3_do (flash_io3_do),
415
416 .flash_io0_di (flash_io0_di),
417 .flash_io1_di (flash_io1_di),
418 .flash_io2_di (flash_io2_di),
419 .flash_io3_di (flash_io3_di)
420 );
421
422 // Wishbone Slave uart
423 wire uart_stb_i;
424 wire uart_ack_o;
425 wire [31:0] uart_dat_o;
Tim Edwardsca2f3182020-10-06 10:05:11 -0400426 wire uart_enabled;
shalanfd13eb52020-08-21 16:48:07 +0200427
428 simpleuart_wb #(
429 .BASE_ADR(UART_BASE_ADR),
430 .CLK_DIV(UART_CLK_DIV),
431 .DATA(UART_DATA)
432 ) simpleuart (
433 // Wishbone Interface
434 .wb_clk_i(wb_clk_i),
435 .wb_rst_i(wb_rst_i),
436
437 .wb_adr_i(cpu_adr_o),
438 .wb_dat_i(cpu_dat_o),
439 .wb_sel_i(cpu_sel_o),
440 .wb_we_i(cpu_we_o),
441 .wb_cyc_i(cpu_cyc_o),
442
443 .wb_stb_i(uart_stb_i),
444 .wb_ack_o(uart_ack_o),
445 .wb_dat_o(uart_dat_o),
446
Tim Edwardsca2f3182020-10-06 10:05:11 -0400447 .uart_enabled(uart_enabled),
shalanfd13eb52020-08-21 16:48:07 +0200448 .ser_tx(ser_tx),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400449 .ser_rx(mgmt_in_data[5])
shalanfd13eb52020-08-21 16:48:07 +0200450 );
451
Tim Edwards04ba17f2020-10-02 22:27:50 -0400452 // Wishbone SPI master
453 wire spi_master_stb_i;
454 wire spi_master_ack_o;
455 wire [31:0] spi_master_dat_o;
456
457 simple_spi_master_wb #(
458 .BASE_ADR(SPI_MASTER_BASE_ADR),
459 .CONFIG(SPI_MASTER_CONFIG),
460 .DATA(SPI_MASTER_DATA)
461 ) simple_spi_master_inst (
462 // Wishbone Interface
463 .wb_clk_i(wb_clk_i),
464 .wb_rst_i(wb_rst_i),
465
466 .wb_adr_i(cpu_adr_o),
467 .wb_dat_i(cpu_dat_o),
468 .wb_sel_i(cpu_sel_o),
469 .wb_we_i(cpu_we_o),
470 .wb_cyc_i(cpu_cyc_o),
471
472 .wb_stb_i(spi_master_stb_i),
473 .wb_ack_o(spi_master_ack_o),
474 .wb_dat_o(spi_master_dat_o),
475
Tim Edwards81153202020-10-09 19:57:04 -0400476 .hk_connect(hk_connect),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400477 .csb(mgmt_out_pre[3]),
478 .sck(mgmt_out_pre[4]),
479 .sdi(mgmt_in_data[1]),
480 .sdo(mgmt_out_pre[2]),
481 .sdoenb(),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400482 .irq(irq_spi_master)
483 );
484
Tim Edwards7be29a22020-10-25 21:50:19 -0400485 wire counter_timer_strobe, counter_timer_offset;
486 wire counter_timer0_enable, counter_timer1_enable;
487 wire counter_timer0_stop, counter_timer1_stop;
Tim Edwards32d05422020-10-19 19:43:52 -0400488
Tim Edwards04ba17f2020-10-02 22:27:50 -0400489 // Wishbone Counter-timer 0
490 wire counter_timer0_stb_i;
491 wire counter_timer0_ack_o;
492 wire [31:0] counter_timer0_dat_o;
493
Tim Edwards7be29a22020-10-25 21:50:19 -0400494 counter_timer_low_wb #(
Tim Edwards04ba17f2020-10-02 22:27:50 -0400495 .BASE_ADR(COUNTER_TIMER0_BASE_ADR),
496 .CONFIG(COUNTER_TIMER0_CONFIG),
497 .VALUE(COUNTER_TIMER0_VALUE),
498 .DATA(COUNTER_TIMER0_DATA)
499 ) counter_timer_0 (
500 // Wishbone Interface
501 .wb_clk_i(wb_clk_i),
502 .wb_rst_i(wb_rst_i),
503
504 .wb_adr_i(cpu_adr_o),
505 .wb_dat_i(cpu_dat_o),
506 .wb_sel_i(cpu_sel_o),
507 .wb_we_i(cpu_we_o),
508 .wb_cyc_i(cpu_cyc_o),
509
510 .wb_stb_i(counter_timer0_stb_i),
511 .wb_ack_o(counter_timer0_ack_o),
512 .wb_dat_o(counter_timer0_dat_o),
Tim Edwards7be29a22020-10-25 21:50:19 -0400513
514 .enable_in(counter_timer1_enable),
515 .stop_in(counter_timer1_stop),
516 .strobe(counter_timer_strobe),
517 .is_offset(counter_timer_offset),
518 .enable_out(counter_timer0_enable),
519 .stop_out(counter_timer0_stop),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400520 .irq(irq_counter_timer0)
521 );
522
523 // Wishbone Counter-timer 1
524 wire counter_timer1_stb_i;
525 wire counter_timer1_ack_o;
526 wire [31:0] counter_timer1_dat_o;
527
Tim Edwards7be29a22020-10-25 21:50:19 -0400528 counter_timer_high_wb #(
Tim Edwards04ba17f2020-10-02 22:27:50 -0400529 .BASE_ADR(COUNTER_TIMER1_BASE_ADR),
530 .CONFIG(COUNTER_TIMER1_CONFIG),
531 .VALUE(COUNTER_TIMER1_VALUE),
532 .DATA(COUNTER_TIMER1_DATA)
533 ) counter_timer_1 (
534 // Wishbone Interface
535 .wb_clk_i(wb_clk_i),
536 .wb_rst_i(wb_rst_i),
537
538 .wb_adr_i(cpu_adr_o),
539 .wb_dat_i(cpu_dat_o),
540 .wb_sel_i(cpu_sel_o),
541 .wb_we_i(cpu_we_o),
542 .wb_cyc_i(cpu_cyc_o),
543
544 .wb_stb_i(counter_timer1_stb_i),
545 .wb_ack_o(counter_timer1_ack_o),
546 .wb_dat_o(counter_timer1_dat_o),
Tim Edwards7be29a22020-10-25 21:50:19 -0400547
548 .enable_in(counter_timer0_enable),
549 .strobe(counter_timer_strobe),
550 .stop_in(counter_timer0_stop),
551 .is_offset(counter_timer_offset),
552 .enable_out(counter_timer1_enable),
553 .stop_out(counter_timer1_stop),
Tim Edwards04ba17f2020-10-02 22:27:50 -0400554 .irq(irq_counter_timer1)
555 );
556
shalanfd13eb52020-08-21 16:48:07 +0200557 // Wishbone Slave GPIO Registers
558 wire gpio_stb_i;
559 wire gpio_ack_o;
560 wire [31:0] gpio_dat_o;
561
562 gpio_wb #(
563 .BASE_ADR(GPIO_BASE_ADR),
564 .GPIO_DATA(GPIO_DATA),
565 .GPIO_ENA(GPIO_ENA),
566 .GPIO_PD(GPIO_PD),
567 .GPIO_PU(GPIO_PU)
568 ) gpio_wb (
569 .wb_clk_i(wb_clk_i),
570 .wb_rst_i(wb_rst_i),
shalanfd13eb52020-08-21 16:48:07 +0200571 .wb_adr_i(cpu_adr_o),
572 .wb_dat_i(cpu_dat_o),
573 .wb_sel_i(cpu_sel_o),
574 .wb_we_i(cpu_we_o),
575 .wb_cyc_i(cpu_cyc_o),
shalanfd13eb52020-08-21 16:48:07 +0200576 .wb_stb_i(gpio_stb_i),
577 .wb_ack_o(gpio_ack_o),
578 .wb_dat_o(gpio_dat_o),
579 .gpio_in_pad(gpio_in_pad),
Tim Edwards32d05422020-10-19 19:43:52 -0400580 .gpio(gpio_out),
581 .gpio_oeb(gpio_outenb),
582 .gpio_pu(gpio_pullup),
583 .gpio_pd(gpio_pulldown)
shalanfd13eb52020-08-21 16:48:07 +0200584 );
585
shalanfd13eb52020-08-21 16:48:07 +0200586 // Wishbone Slave System Control Register
587 wire sys_stb_i;
588 wire sys_ack_o;
589 wire [31:0] sys_dat_o;
590
591 sysctrl_wb #(
592 .BASE_ADR(SYS_BASE_ADR),
Tim Edwards32d05422020-10-19 19:43:52 -0400593 .PWRGOOD(PWRGOOD),
594 .CLK_OUT(CLK_OUT),
shalanfd13eb52020-08-21 16:48:07 +0200595 .TRAP_OUT(TRAP_OUT),
Tim Edwards32d05422020-10-19 19:43:52 -0400596 .IRQ_SRC(IRQ_SRC)
shalanfd13eb52020-08-21 16:48:07 +0200597 ) sysctrl (
598 .wb_clk_i(wb_clk_i),
599 .wb_rst_i(wb_rst_i),
600
601 .wb_adr_i(cpu_adr_o),
602 .wb_dat_i(cpu_dat_o),
603 .wb_sel_i(cpu_sel_o),
604 .wb_we_i(cpu_we_o),
605 .wb_cyc_i(cpu_cyc_o),
606
607 .wb_stb_i(sys_stb_i),
608 .wb_ack_o(sys_ack_o),
609 .wb_dat_o(sys_dat_o),
610
Tim Edwards05ad4fc2020-10-19 22:12:33 -0400611 .usr1_vcc_pwrgood(mprj_vcc_pwrgood),
612 .usr2_vcc_pwrgood(mprj2_vcc_pwrgood),
613 .usr1_vdd_pwrgood(mprj_vdd_pwrgood),
614 .usr2_vdd_pwrgood(mprj2_vdd_pwrgood),
shalanfd13eb52020-08-21 16:48:07 +0200615 .trap_output_dest(trap_output_dest),
Tim Edwards32d05422020-10-19 19:43:52 -0400616 .clk1_output_dest(clk1_output_dest),
617 .clk2_output_dest(clk2_output_dest),
618 .irq_7_inputsrc(irq_7_inputsrc),
619 .irq_8_inputsrc(irq_8_inputsrc)
shalanfd13eb52020-08-21 16:48:07 +0200620 );
621
622 // Logic Analyzer
623 wire la_stb_i;
624 wire la_ack_o;
625 wire [31:0] la_dat_o;
626
627 la_wb #(
628 .BASE_ADR(LA_BASE_ADR),
629 .LA_DATA_0(LA_DATA_0),
630 .LA_DATA_1(LA_DATA_1),
631 .LA_DATA_3(LA_DATA_3),
632 .LA_ENA_0(LA_ENA_0),
633 .LA_ENA_1(LA_ENA_1),
634 .LA_ENA_2(LA_ENA_2),
635 .LA_ENA_3(LA_ENA_3)
636 ) la (
637 .wb_clk_i(wb_clk_i),
638 .wb_rst_i(wb_rst_i),
639
640 .wb_adr_i(cpu_adr_o),
641 .wb_dat_i(cpu_dat_o),
642 .wb_sel_i(cpu_sel_o),
643 .wb_we_i(cpu_we_o),
644 .wb_cyc_i(cpu_cyc_o),
645
646 .wb_stb_i(la_stb_i),
647 .wb_ack_o(la_ack_o),
648 .wb_dat_o(la_dat_o),
649
650 .la_data(la_output),
shalan0d14e6e2020-08-31 16:50:48 +0200651 .la_data_in(la_input),
652 .la_oen(la_oen)
shalanfd13eb52020-08-21 16:48:07 +0200653 );
654
Tim Edwards6d9739d2020-10-19 11:00:49 -0400655 // WB Slave User Project Control
shalan0d14e6e2020-08-31 16:50:48 +0200656 wire mprj_ctrl_stb_i;
657 wire mprj_ctrl_ack_o;
658 wire [31:0] mprj_ctrl_dat_o;
Tim Edwards9eda80d2020-10-08 21:36:44 -0400659 wire [MPRJ_IO_PADS-1:0] mgmt_out_pre;
Tim Edwardsca2f3182020-10-06 10:05:11 -0400660
661 // Bits assigned to specific functions as outputs prevent the
662 // mprj GPIO-as-output from applying data when that function
663 // is active
664
Tim Edwards32d05422020-10-19 19:43:52 -0400665 assign mgmt_out_data[MPRJ_IO_PADS-1:16] = mgmt_out_pre[MPRJ_IO_PADS-1:16];
666
667 // Routing of output monitors (PLL, trap, clk1, clk2)
668 assign mgmt_out_data[15] = clk2_output_dest ? user_clk : mgmt_out_pre[15];
669 assign mgmt_out_data[14] = clk1_output_dest ? clk : mgmt_out_pre[14];
670 assign mgmt_out_data[13] = trap_output_dest ? trap : mgmt_out_pre[13];
671
672 assign mgmt_out_data[12:7] = mgmt_out_pre[12:7];
Tim Edwardsca2f3182020-10-06 10:05:11 -0400673 assign mgmt_out_data[6] = uart_enabled ? ser_tx : mgmt_out_pre[6];
674 assign mgmt_out_data[5:0] = mgmt_out_pre[5:0];
shalan0d14e6e2020-08-31 16:50:48 +0200675
676 mprj_ctrl_wb #(
677 .BASE_ADR(MPRJ_CTRL_ADR),
678 .IO_PADS(MPRJ_IO_PADS),
Tim Edwardsc18c4742020-10-03 11:26:39 -0400679 .PWR_PADS(MPRJ_PWR_PADS)
shalan0d14e6e2020-08-31 16:50:48 +0200680 ) mprj_ctrl (
681 .wb_clk_i(wb_clk_i),
682 .wb_rst_i(wb_rst_i),
683
684 .wb_adr_i(cpu_adr_o),
685 .wb_dat_i(cpu_dat_o),
686 .wb_sel_i(cpu_sel_o),
687 .wb_we_i(cpu_we_o),
688 .wb_cyc_i(cpu_cyc_o),
689 .wb_stb_i(mprj_ctrl_stb_i),
690 .wb_ack_o(mprj_ctrl_ack_o),
691 .wb_dat_o(mprj_ctrl_dat_o),
692
Tim Edwards04ba17f2020-10-02 22:27:50 -0400693 .serial_clock(mprj_io_loader_clock),
694 .serial_resetn(mprj_io_loader_resetn),
695 .serial_data_out(mprj_io_loader_data),
Tim Edwardsca2f3182020-10-06 10:05:11 -0400696 .mgmt_gpio_out(mgmt_out_pre),
697 .mgmt_gpio_in(mgmt_in_data)
shalan0d14e6e2020-08-31 16:50:48 +0200698 );
699
shalanfd13eb52020-08-21 16:48:07 +0200700 // Wishbone Slave RAM
701 wire mem_stb_i;
702 wire mem_ack_o;
703 wire [31:0] mem_dat_o;
704
705 mem_wb #(
706 .MEM_WORDS(MEM_WORDS)
707 ) soc_mem (
708 .wb_clk_i(wb_clk_i),
709 .wb_rst_i(wb_rst_i),
710
711 .wb_adr_i(cpu_adr_o),
712 .wb_dat_i(cpu_dat_o),
713 .wb_sel_i(cpu_sel_o),
714 .wb_we_i(cpu_we_o),
715 .wb_cyc_i(cpu_cyc_o),
716
717 .wb_stb_i(mem_stb_i),
718 .wb_ack_o(mem_ack_o),
719 .wb_dat_o(mem_dat_o)
720 );
721
Manar14d35ac2020-10-21 22:47:15 +0200722 // Wishbone Slave Synthesized RAM
723 wire mem_synth_stb_i;
724 wire mem_synth_ack_o;
725 wire [31:0] mem_synth_dat_o;
726
727 mem_synth_wb #(
728 .MEM_WORDS(MEM_SYNTH_WORDS)
729 ) soc_mem_synth (
730 .wb_clk_i(wb_clk_i),
731 .wb_rst_i(wb_rst_i),
732 .wb_adr_i(cpu_adr_o),
733 .wb_dat_i(cpu_dat_o),
734 .wb_sel_i(cpu_sel_o),
735 .wb_we_i(cpu_we_o),
736 .wb_cyc_i(cpu_cyc_o),
737 .wb_stb_i(mem_synth_stb_i),
738 .wb_ack_o(mem_synth_ack_o),
739 .wb_dat_o(mem_synth_dat_o)
740 );
741
shalanfd13eb52020-08-21 16:48:07 +0200742 // Wishbone intercon logic
743 wb_intercon #(
744 .AW(ADR_WIDTH),
745 .DW(DAT_WIDTH),
746 .NS(NUM_SLAVES),
747 .ADR_MASK(ADR_MASK),
748 .SLAVE_ADR(SLAVE_ADR)
749 ) intercon (
750 // Master Interface
751 .wbm_adr_i(cpu_adr_o),
752 .wbm_stb_i(cpu_stb_o),
753 .wbm_dat_o(cpu_dat_i),
754 .wbm_ack_o(cpu_ack_i),
755
756 // Slaves Interface
Manar98a7adc2020-10-19 23:21:36 +0200757 .wbs_stb_o({ sys_stb_i, spimemio_cfg_stb_i,
Tim Edwards04ba17f2020-10-02 22:27:50 -0400758 mprj_stb_o, mprj_ctrl_stb_i, la_stb_i,
759 spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
760 gpio_stb_i, uart_stb_i,
Manar14d35ac2020-10-21 22:47:15 +0200761 spimemio_flash_stb_i, mem_synth_stb_i, mem_stb_i }),
Manar98a7adc2020-10-19 23:21:36 +0200762 .wbs_dat_i({ sys_dat_o, spimemio_cfg_dat_o,
Tim Edwards04ba17f2020-10-02 22:27:50 -0400763 mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
764 spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
765 gpio_dat_o, uart_dat_o,
Manar14d35ac2020-10-21 22:47:15 +0200766 spimemio_flash_dat_o,mem_synth_dat_o, mem_dat_o }),
Manar98a7adc2020-10-19 23:21:36 +0200767 .wbs_ack_i({ sys_ack_o, spimemio_cfg_ack_o,
Tim Edwards04ba17f2020-10-02 22:27:50 -0400768 mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
769 spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
770 gpio_ack_o, uart_ack_o,
Manar14d35ac2020-10-21 22:47:15 +0200771 spimemio_flash_ack_o, mem_synth_ack_o, mem_ack_o })
shalanfd13eb52020-08-21 16:48:07 +0200772 );
773
shalanfd13eb52020-08-21 16:48:07 +0200774endmodule
775
shalanfd13eb52020-08-21 16:48:07 +0200776// Implementation note:
777// Replace the following two modules with wrappers for your SRAM cells.
Tim Edwardsef8312e2020-09-22 17:20:06 -0400778
Tim Edwards04ba17f2020-10-02 22:27:50 -0400779module mgmt_soc_regs (
shalanfd13eb52020-08-21 16:48:07 +0200780 input clk, wen,
781 input [5:0] waddr,
782 input [5:0] raddr1,
783 input [5:0] raddr2,
784 input [31:0] wdata,
785 output [31:0] rdata1,
786 output [31:0] rdata2
787);
788 reg [31:0] regs [0:31];
789
790 always @(posedge clk)
791 if (wen) regs[waddr[4:0]] <= wdata;
792
793 assign rdata1 = regs[raddr1[4:0]];
794 assign rdata2 = regs[raddr2[4:0]];
795endmodule