| commit | fe9c3bb707a0e10e9b31adc0352bce2ffaa494cb | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Thu Nov 26 15:29:48 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Thu Nov 26 15:29:48 2020 +0200 |
| tree | 84831d02cbdd4cdc71e78b8eb95615b561fc2fde | |
| parent | fc7bd3c590405bdcde63957db5babf452e4d7866 [diff] [blame] |
Add two more missing USE_POWER_PINS guards
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v index d285a91..0c6840d 100644 --- a/verilog/rtl/mgmt_protect.v +++ b/verilog/rtl/mgmt_protect.v
@@ -15,6 +15,7 @@ /*----------------------------------------------------------------------*/ module mgmt_protect ( +`ifdef USE_POWER_PINS inout vccd, inout vssd, inout vccd1, @@ -25,6 +26,7 @@ inout vssa1, inout vdda2, inout vssa2, +`endif input caravel_clk, input caravel_clk2,