Add two more missing USE_POWER_PINS guards
diff --git a/verilog/rtl/mgmt_protect.v b/verilog/rtl/mgmt_protect.v
index d285a91..0c6840d 100644
--- a/verilog/rtl/mgmt_protect.v
+++ b/verilog/rtl/mgmt_protect.v
@@ -15,6 +15,7 @@
 /*----------------------------------------------------------------------*/
 
 module mgmt_protect (
+`ifdef USE_POWER_PINS
     inout	  vccd,
     inout	  vssd,
     inout	  vccd1,
@@ -25,6 +26,7 @@
     inout	  vssa1,
     inout	  vdda2,
     inout	  vssa2,
+`endif
 
     input 	  caravel_clk,
     input 	  caravel_clk2,