Made a few testbench corrections and added the missing OEB lines from the
user project. All existing testbench tests are now passing.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 742977c..4c2a6b9 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -54,11 +54,16 @@
// IOs
input [IO_PADS-1:0] io_in,
- output [IO_PADS-1:0] io_out
+ output [IO_PADS-1:0] io_out,
+ output [IO_PADS-1:0] io_oeb
);
wire clk;
wire rst;
+ wire [IO_PADS-1:0] io_in;
+ wire [IO_PADS-1:0] io_out;
+ wire [IO_PADS-1:0] io_oeb;
+
wire [31:0] rdata;
wire [31:0] wdata;
wire [BITS-1:0] count;
@@ -75,6 +80,7 @@
// IO
assign io_out = count;
+ assign io_oeb = {(IO_PADS-1){rst}};
// LA
assign la_data_out = {{(127-BITS){1'b0}}, count};
