commit ef2b68d44d85b1be0eb2b972418158fbd03fc57c
author Tim Edwards <tim@opencircuitdesign.com> Sun Oct 11 17:00:44 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Sun Oct 11 17:00:44 2020 -0400
tree 197e9b8f073ce5b65c5ed99f92a9f012e496ba39
parent 4286ae1893985e072316ab95a6dee39be3a7eff2

Made a few testbench corrections and added the missing OEB lines from the
user project.  All existing testbench tests are now passing.

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 3c711fd..463f127 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -413,7 +413,8 @@
 		.la_oen (la_oen),
 		// IO Pads
 		.io_in (user_io_in),
-    		.io_out(user_io_out)
+    		.io_out(user_io_out),
+    		.io_oeb(user_io_oeb)
 	);
 
 	/*--------------------------------------*/