Minor RTL fixes, switching to wrapped GPIOV2
- use USER2_ABUTMENT_PINS for the second of the vssio and vddio pads
- do core-facing power-to-signal connections using the auto-router
- fix corner pad power connections and keep them for LVS purposes
- add a bunch of missing USE_POWER_PINS guards
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v
index 5546130..3445aa0 100644
--- a/verilog/rtl/user_proj_example.v
+++ b/verilog/rtl/user_proj_example.v
@@ -23,6 +23,7 @@
module user_proj_example #(
parameter BITS = 32
)(
+`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
@@ -31,6 +32,7 @@
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
+`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
