Various corrections to simplify the user project I/O wiring
connections into the management area. Corrected testbenches
for hkspi, mem, uart, perf, and gpio.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 58dd692..a39fdea 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -319,9 +319,11 @@
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
.mgmt_in_data(mgmt_io_in),
- .mgmt_outz_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
- .mgmt_out_data({mgmt_io_nc1, sdo_out, jtag_out}),
- .mgmt_oeb_data({mgmt_io_nc3, sdo_outenb, jtag_outenb}),
+ .mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
+ .sdo_out(sdo_out),
+ .sdo_outenb(sdo_outenb),
+ .jtag_out(jtag_out),
+ .jtag_outenb(jtag_outenb),
// Mega Project Slave ports (WB MI A)
.mprj_cyc_o(mprj_cyc_o_core),
.mprj_stb_o(mprj_stb_o_core),
