Added a behavioral model for the ring oscillator, and a testbench
for running the PLL (in behavioral mode), specifically for switching
to and from PLL bypass mode from the processor itself.
diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index ddc553d..d4f7a4c 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -99,9 +99,13 @@
if (prep == 3'b111) begin
if (sum > div) begin
- tval <= tval + 1;
+ if (tval < 127) begin
+ tval <= tval + 1;
+ end
end else if (sum < div) begin
- tval <= tval - 1;
+ if (tval > 0) begin
+ tval <= tval - 1;
+ end
end
end
end else begin
