Revised the mprj_ctrl to treat the power control as a single bit
read/write per power domain, not part of the serial load chain.
This greatly simplifies the code in the mprj_ctrl module. Also
brought the power control pins up to the top level, in case we
want to use them for internally enabling/disabling the user area
power supplies (may be an experimental function on one or more
versions). Also: Corrected a few entries in the defs.h header
file, and added definitions for the bit fields in a number of
registers that have individual bitmask entries.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index b55ec62..675a873 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -72,6 +72,7 @@
inout gpio, // Used for external LDO control
inout [`MPRJ_IO_PADS-1:0] mprj_io,
+ output [`MPRJ_PWR_PADS-1:0] pwr_ctrl_out,
input clock, // CMOS core clock input, not a crystal
input resetb,
@@ -367,6 +368,7 @@
.mprj_io_loader_data(mprj_io_loader_data),
.mgmt_in_data(mgmt_io_in),
.mgmt_out_data({mgmt_io_in[(`MPRJ_IO_PADS-1):2], mgmt_io_nc2}),
+ .pwr_ctrl_out(pwr_ctrl_out),
.sdo_out(sdo_out),
.sdo_outenb(sdo_outenb),
.jtag_out(jtag_out),
