Added GL simulations
- updated mgmt_core gl netlist to the one with tri-state buffers
- updated mgmt_core and digital_pll power pin names to match the names in the powered GL netlist
diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 2f3fc2a..9840a7d 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -7,14 +7,14 @@
module digital_pll(
`ifdef USE_POWER_PINS
- vdd,
- vss,
+ VPWR,
+ VGND,
`endif
resetb, enable, osc, clockp, div, dco, ext_trim);
`ifdef USE_POWER_PINS
- input vdd;
- input vss;
+ input VPWR;
+ input VGND;
`endif
input resetb; // Sense negative reset
