Added testbench files for project verification.
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile b/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile
new file mode 100644
index 0000000..350b2f9
--- /dev/null
+++ b/verilog/dv/caravel/ghazi_top_dffram_csv/Makefile
@@ -0,0 +1,18 @@
+# ---- Test patterns for project striVe ----
+
+.SUFFIXES:
+.SILENT: clean all
+
+PATTERNS = test_1
+
+all: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make -f Makefile $${i}.vcd &> verify.log && grep Monitor verify.log) ; \
+ done
+
+clean: ${PATTERNS}
+ for i in ${PATTERNS}; do \
+ ( cd $$i && make clean ) ; \
+ done
+
+.PHONY: clean all
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile
new file mode 100644
index 0000000..6cb9bc4
--- /dev/null
+++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/Makefile
@@ -0,0 +1,42 @@
+FIRMWARE_PATH = ../..
+RTL_PATH = ../../../../rtl
+IP_PATH = ../../../../ip
+BEHAVIOURAL_MODELS = ../../
+
+GCC_PATH?=/ef/apps/bin
+GCC_PREFIX?=riscv32-unknown-elf
+PDK_PATH?=/ef/tech/SW/sky130A
+
+.SUFFIXES:
+
+PATTERN = test_1
+
+all: ${PATTERN:=.vcd}
+
+hex: ${PATTERN:=.hex}
+
+%.vvp: %_tb.v %.hex
+ iverilog -DFUNCTIONAL -I $(BEHAVIOURAL_MODELS) \
+ -I $(PDK_PATH) -I $(IP_PATH) -I $(RTL_PATH) \
+ -o $@ $<
+
+%.vcd: %.vvp
+ vvp $<
+
+%.elf: %.c $(FIRMWARE_PATH)/sections.lds $(FIRMWARE_PATH)/start.s
+ ${GCC_PATH}/${GCC_PREFIX}-gcc -march=rv32imc -Wl,-Bstatic,-T,$(FIRMWARE_PATH)/sections.lds,--strip-debug -ffreestanding -nostdlib -o $@ $(FIRMWARE_PATH)/start.s $<
+
+%.hex: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O verilog $< $@
+ # to fix flash base address
+ sed -i 's/@10000000/@00000000/g' $@
+
+%.bin: %.elf
+ ${GCC_PATH}/${GCC_PREFIX}-objcopy -O binary $< /dev/stdout | tail -c +1048577 > $@
+
+# ---- Clean ----
+
+clean:
+ rm -f *.elf *.hex *.bin *.vvp *.vcd *.log
+
+.PHONY: clean hex all
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c
new file mode 100644
index 0000000..7429a92
--- /dev/null
+++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1.c
@@ -0,0 +1,34 @@
+#include "../../defs.h"
+
+void main()
+{
+ // reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_5 = GPIO_MODE_USER_STD_INPUT_NOPULL;
+ // reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ // reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_6 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
+ reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
+
+ reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
+
+ reg_mprj_xfer = 1;
+ while(reg_mprj_xfer == 1);
+
+ reg_la1_ena = 0x00000000;
+ reg_la1_data = 0x0000015C;
+
+ reg_la0_ena = 0x00000000;
+ reg_la0_data = 0x00000001;
+ reg_la0_data = 0x00000000;
+ reg_mprj_datah = 0x20;
+
+}
diff --git a/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v
new file mode 100644
index 0000000..ea18d61
--- /dev/null
+++ b/verilog/dv/caravel/ghazi_top_dffram_csv/test_1/test_1_tb.v
@@ -0,0 +1,151 @@
+`default_nettype none
+
+`timescale 1 ns / 1 ps
+
+`include "caravel.v"
+`include "spiflash.v"
+`include "tbprog.v"
+
+module test_1_tb;
+ reg clock;
+ reg RSTB;
+ reg power1, power2;
+ reg power3, power4;
+
+ wire gpio;
+ wire [37:0] mprj_io;
+
+ wire [6:0] mprj_io_0;
+ wire mprj_ready;
+
+ assign mprj_io_0 = mprj_io[12:6];
+ assign mprj_ready = mprj_io[37];
+
+
+ // External clock is used by default. Make this artificially fast for the
+ // simulation. Normally this would be a slow clock and the digital PLL
+ // would be the fast clock.
+
+ always #12.5 clock <= (clock === 1'b0);
+
+ initial begin
+ clock = 0;
+ end
+
+ initial begin
+ $dumpfile("test_1.vcd");
+ $dumpvars(0, test_1_tb);
+
+ // Repeat cycles of 1000 clock edges as needed to complete testbench
+ repeat (300) begin
+ repeat (1000) @(posedge clock);
+ // $display("+1000 cycles");
+ end
+ $display("%c[1;31m",27);
+ $display ("Monitor: Timeout, Test Mega-Project IO Ports (RTL) Failed");
+ $display("%c[0m",27);
+ $finish;
+ end
+
+ initial begin
+ // Observe Output pins [12:6]
+ wait(mprj_ready == 1'b1);
+ wait(mprj_io_0 == 7'h01);
+ wait(mprj_io_0 == 7'h03);
+ wait(mprj_io_0 == 7'h05);
+ wait(mprj_io_0 == 7'h07);
+ wait(mprj_io_0 == 7'h13);
+ wait(mprj_io_0 == 7'h55);
+ wait(mprj_io_0 == 7'h7F);
+
+ $display("Monitor: Test 1 Mega-Project IO (RTL) Passed");
+ $finish;
+ end
+
+ initial begin
+ RSTB <= 1'b0;
+ #2000;
+ RSTB <= 1'b1; // Release reset
+ end
+
+ initial begin // Power-up sequence
+ power1 <= 1'b0;
+ power2 <= 1'b0;
+ power3 <= 1'b0;
+ power4 <= 1'b0;
+ #200;
+ power1 <= 1'b1;
+ #200;
+ power2 <= 1'b1;
+ #200;
+ power3 <= 1'b1;
+ #200;
+ power4 <= 1'b1;
+ end
+
+ always @(mprj_io) begin
+ #1 $display("MPRJ-IO state = 0x%0h ", mprj_io_0);
+ end
+
+ wire flash_csb;
+ wire flash_clk;
+ wire flash_io0;
+ wire flash_io1;
+ wire r_Rx_Serial;
+ assign mprj_io[5] = r_Rx_Serial;
+
+
+
+ wire VDD1V8;
+ wire VDD3V3;
+ wire VSS;
+
+ assign VDD3V3 = power1;
+ assign VDD1V8 = power2;
+ assign VSS = 1'b0;
+
+ caravel uut (
+ .vddio (VDD3V3),
+ .vssio (VSS),
+ .vdda (VDD3V3),
+ .vssa (VSS),
+ .vccd (VDD1V8),
+ .vssd (VSS),
+ .vdda1 (VDD3V3),
+ .vdda2 (VDD3V3),
+ .vssa1 (VSS),
+ .vssa2 (VSS),
+ .vccd1 (VDD1V8),
+ .vccd2 (VDD1V8),
+ .vssd1 (VSS),
+ .vssd2 (VSS),
+ .clock (clock),
+ .gpio (gpio),
+ .mprj_io (mprj_io),
+ .flash_csb(flash_csb),
+ .flash_clk(flash_clk),
+ .flash_io0(flash_io0),
+ .flash_io1(flash_io1),
+ .resetb (RSTB)
+ );
+
+ spiflash #(
+ .FILENAME("test_1.hex")
+ ) spiflash (
+ .csb(flash_csb),
+ .clk(flash_clk),
+ .io0(flash_io0),
+ .io1(flash_io1),
+ .io2(), // not used
+ .io3() // not used
+ );
+
+ tbprog #(
+ .FILENAME("../hex/test_1.hex")
+ ) prog_uut (
+ .mprj_ready (mprj_ready),
+ .r_Rx_Serial (r_Rx_Serial)
+ );
+
+endmodule
+`default_nettype wire
