Changed user project instance is wrapper module.
diff --git a/verilog/rtl/user_project_wrapper.v b/verilog/rtl/user_project_wrapper.v
index 0b23a50..d26d18d 100644
--- a/verilog/rtl/user_project_wrapper.v
+++ b/verilog/rtl/user_project_wrapper.v
@@ -64,7 +64,7 @@
/* User project is instantiated here */
/*--------------------------------------*/
- user_proj_example mprj (
+ ghazi_top_dffram_csv mprj (
`ifdef USE_POWER_PINS
.vdda1(vdda1), // User area 1 3.3V power
.vdda2(vdda2), // User area 2 3.3V power