commit 589a528c7eec14294621d99747bb0850dcfae114
author manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:06:48 2020 +0200
committer manarabdelaty <manarabdelatty@aucegypt.edu> Sat Dec 05 01:06:48 2020 +0200
tree 64a4cc6b3d0f53e1ccfdff6560449668d7b995fc
parent ea96b3a6c6fa5e4c7236be9292cda5f9774c128f

RTL updates to fix gl sim

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 51d6529..08a6241 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -550,8 +550,8 @@
     // SDO).  The rest are configured to be default (input).
 
     gpio_control_block #(
-	.DM_INIT(3'b110),	// Mode = output, strong up/down
-	.OENB_INIT(1'b1)	// Enable output signaling from wire
+	.DM_INIT(`DM_INIT),	// Mode = output, strong up/down
+	.OENB_INIT(`OENB_INIT)	// Enable output signaling from wire
     ) gpio_control_bidir [1:0] (
     	`ifdef USE_POWER_PINS
 			.vccd(vccd),