| commit | 581068fea64d0d978f060a259cfbb2756bc88e90 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Thu Nov 19 12:45:25 2020 -0500 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Thu Nov 19 12:45:25 2020 -0500 |
| tree | 3dd85a0d3aa275b8d6dd4c9d828839a8a5eb25ac | |
| parent | 09a7237e644d417d35af7f586a8e90c0ba013794 [diff] [blame] |
Corrected the mess caused by introducing default_nettype none into the design verification netlists. Also cleaned up the broken power-on-reset signaling, and added connections from the user space to the I/O pad direct-to-pad analog signal pins.
diff --git a/verilog/rtl/user_proj_example.v b/verilog/rtl/user_proj_example.v index 6c1c117..5546130 100644 --- a/verilog/rtl/user_proj_example.v +++ b/verilog/rtl/user_proj_example.v
@@ -152,3 +152,4 @@ endgenerate endmodule +`default_nettype wire