commit 581068fea64d0d978f060a259cfbb2756bc88e90
author Tim Edwards <tim@opencircuitdesign.com> Thu Nov 19 12:45:25 2020 -0500
committer Tim Edwards <tim@opencircuitdesign.com> Thu Nov 19 12:45:25 2020 -0500
tree 3dd85a0d3aa275b8d6dd4c9d828839a8a5eb25ac
parent 09a7237e644d417d35af7f586a8e90c0ba013794

Corrected the mess caused by introducing default_nettype none into the design
verification netlists.  Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.

verilog/rtl/simpleuart.v

diff --git a/verilog/rtl/simpleuart.v b/verilog/rtl/simpleuart.v
index 66e1915..4fe9f0c 100644
--- a/verilog/rtl/simpleuart.v
+++ b/verilog/rtl/simpleuart.v
@@ -220,3 +220,4 @@
         end
     end
 endmodule
+`default_nettype wire