Corrected the mess caused by introducing default_nettype none into the design
verification netlists. Also cleaned up the broken power-on-reset signaling,
and added connections from the user space to the I/O pad direct-to-pad analog
signal pins.
diff --git a/verilog/rtl/mprj_ctrl.v b/verilog/rtl/mprj_ctrl.v
index 6b17fe2..b31c23a 100644
--- a/verilog/rtl/mprj_ctrl.v
+++ b/verilog/rtl/mprj_ctrl.v
@@ -124,6 +124,7 @@
wire pwr_data_sel;
wire xfer_sel;
wire busy;
+ wire selected;
wire [`MPRJ_IO_PADS-1:0] io_ctrl_sel;
reg [31:0] iomem_rdata_pre;
@@ -365,3 +366,4 @@
end
endmodule
+`default_nettype wire
