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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-018 / 49fc48958dfa2ab07dde68fb9a4c8316f1292414
commit49fc48958dfa2ab07dde68fb9a4c8316f1292414[log] [tgz]
authorMohamed Shalan <mshalan@aucegypt.edu>Mon Aug 31 16:56:48 2020 +0200
committerGitHub <noreply@github.com>Mon Aug 31 16:56:48 2020 +0200
treec34be4189006a283c39494eaf0238744f39558aa
parent65a348774751795cb58fcf7d2764492fde595963 [diff]
Update README.md
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README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.