Made a change to all of the testbench Makefiles to define PDK_PATH as the
root of the PDK, and pass this to iverilog with the -I option. This lets
the PDK location be passed to "make" when the testbench is run, and lets
the top-level verilog not contain absolute paths to the PDK. Also:
replaced the s8iom0s8.v with sky130_fd_io.v, which is currently just a
hack since the pad names have not changed; I have just copied my I/O
library file to the new location and file name.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 79830be..3c711fd 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -22,21 +22,15 @@
`include "pads.v"
-/* To be removed when sky130_fd_io is available */
-// `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/s8iom0s8.v"
-// `include "/ef/tech/SW/EFS8A/libs.ref/verilog/s8iom0s8/power_pads_lib.v"
-// `include "/ef/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
-// `include "/ef/tech/SW/sky130A/libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
+/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
-/* Local only, please remove */
-// `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
-// `include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_io/verilog/power_pads_lib.v"
-`include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/s8iom0s8.v"
-// `include "/home/tim/projects/efabless/tech/SW/EFS8A/libs.ref/s8iom0s8/verilog/power_pads_lib.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
-`include "/home/tim/projects/efabless/tech/SW/sky130A/libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
+`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
+// `include "libs.ref/sky130_fd_io/verilog/power_pads_lib.v"
+
+`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
+`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
`include "mgmt_soc.v"
`include "housekeeping_spi.v"
