Added two additional features: (1) Timer chaining, which allows one
timer to be clocked from the output of the other, forming a 64-bit
timer, and (2) User power-good signal, memory-mapped so that the state
of the user's 1.8V power domain can be assessed (should have the same
for the 3.3V domains). Also: The routing of the PLL output and trap
and IRQ inputs was moved from the single gpio pin to additional bits
in the user space, and an additional output routing was made for the
secondary clock.
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index e5af073..fbaaa5c 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -344,6 +344,8 @@
.la_output(la_output_core),
.la_oen(la_oen),
// User Project IO Control
+ .mprj_pwrgood(mprj_pwrgood),
+ .mprj2_pwrgood(mprj2_pwrgood),
.mprj_io_loader_resetn(mprj_io_loader_resetn),
.mprj_io_loader_clock(mprj_io_loader_clock),
.mprj_io_loader_data(mprj_io_loader_data),
@@ -389,6 +391,8 @@
wire [3:0] mprj_sel_o_user;
wire [31:0] mprj_adr_o_user;
wire [31:0] mprj_dat_o_user;
+ wire mprj_pwrgood;
+ wire mprj2_pwrgood;
mgmt_protect mgmt_buffers (
.vccd(vccd),
@@ -417,7 +421,9 @@
.mprj_sel_o_user(mprj_sel_o_user),
.mprj_adr_o_user(mprj_adr_o_user),
.mprj_dat_o_user(mprj_dat_o_user),
- .la_data_in_mprj(la_data_in_mprj)
+ .la_data_in_mprj(la_data_in_mprj),
+ .user1_powergood(mprj_pwrgood),
+ .user2_powergood(mprj2_pwrgood)
);
