| commit | 2517fa8538d616830340da4984502271fb902f19 | [log] [tgz] |
|---|---|---|
| author | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Sun Nov 08 23:34:41 2020 +0200 |
| committer | Ahmed Ghazy <ax3ghazy@aucegypt.edu> | Sun Nov 08 23:34:41 2020 +0200 |
| tree | a62a20c21e5797527580bf0a50da0a86e6e3325e | |
| parent | a4f9b52d71dbb86678d0743e25b8229126b5da64 [diff] [blame] |
Add USE_CUSTOM_DFFRAM guard - enable it to use the small custom DFFRAM; otherwise, use the generic RAM verilog model - also updated the aspect ratio of the custom DFFRAM
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index d7c123f..23fb906 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v
@@ -42,6 +42,7 @@ `include "clock_div.v" `include "simple_por.v" `include "storage_bridge_wb.v" +`include "DFFRAM.v" `include "sram_1rw1r_32_256_8_sky130.v" `include "storage.v"