Add a global defines.v and rely less on parameters
- This is mainly to avoid "accidents" with default parameter values
diff --git a/verilog/rtl/mem_synth_wb.v b/verilog/rtl/mem_synth_wb.v
index d54ddf6..c4a1cc4 100644
--- a/verilog/rtl/mem_synth_wb.v
+++ b/verilog/rtl/mem_synth_wb.v
@@ -1,6 +1,4 @@
-module mem_synth_wb #(
- parameter integer MEM_WORDS = 1024
-)(
+module mem_synth_wb (
input wb_clk_i,
input wb_rst_i,
@@ -37,9 +35,7 @@
end
end
- soc_mem_synth # (
- .MEM_WORDS(MEM_WORDS)
- ) mem (
+ soc_mem_synth mem (
.clk(wb_clk_i),
.ena(valid),
.wen(wen),
@@ -50,9 +46,7 @@
endmodule
-module soc_mem_synth #(
- parameter integer MEM_WORDS = 2048
-)(
+module soc_mem_synth (
input clk,
input ena,
input [3:0] wen,
@@ -62,7 +56,7 @@
);
reg [31:0] rdata;
- reg [31:0] mem [0:MEM_WORDS-1];
+ reg [31:0] mem [0:`MEM_SYNTH_WORDS-1];
always @(posedge clk) begin
if (ena == 1'b1) begin
@@ -74,4 +68,4 @@
end
end
-endmodule
\ No newline at end of file
+endmodule
