commit 21a9aac19537bf1a1e90e356d67a6b0e05bf1091
author Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
committer Tim Edwards <tim@opencircuitdesign.com> Mon Oct 12 22:05:18 2020 -0400
tree 96dea37f5673c8e442119bd5fe9ec8416cd5d51c
parent e2ef673adf739e8eec22d45574b754a0269b14e3

Testbench simulations are now all working correctly with the pre-release
version of sky130_fd_io.

verilog/rtl/caravel.v

diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 10bcde8..433dd91 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -390,12 +390,11 @@
 	wire [31:0] mprj_dat_o_user;
 
 	mgmt_protect mgmt_buffers (
-	    `ifdef LVS
 		.vccd(vccd),
 		.vssd(vssd),
 		.vccd1(vccd1),
 		.vssd1(vssd1),
-	    `endif
+
 		.caravel_clk(caravel_clk),
 		.caravel_clk2(caravel_clk2),
 		.caravel_rstn(caravel_rstn),
@@ -429,16 +428,15 @@
 	    .IO_PADS(`MPRJ_IO_PADS),
 	    .PWR_PADS(`MPRJ_PWR_PADS)
 	) mprj ( 
-	    `ifdef LVS
-		vdda1,	// User area 1 3.3V power
-		vdda2,	// User area 2 3.3V power
-		vssa1,	// User area 1 analog ground
-		vssa2,	// User area 2 analog ground
-		vccd1,	// User area 1 1.8V power
-		vccd2,	// User area 2 1.8V power
-		vssa1,	// User area 1 digital ground
-		vssa2,	// User area 2 digital ground
-	    `endif
+		.vdda1(vdda1),	// User area 1 3.3V power
+		.vdda2(vdda2),	// User area 2 3.3V power
+		.vssa1(vssa1),	// User area 1 analog ground
+		.vssa2(vssa2),	// User area 2 analog ground
+		.vccd1(vccd1),	// User area 1 1.8V power
+		.vccd2(vccd2),	// User area 2 1.8V power
+		.vssd1(vssd1),	// User area 1 digital ground
+		.vssd2(vssd2),	// User area 2 digital ground
+
     		.wb_clk_i(mprj_clock),
     		.wb_rst_i(!mprj_resetn),
 		// MGMT SoC Wishbone Slave 
@@ -564,13 +562,11 @@
     );
 
     sky130_fd_sc_hvl__lsbufhv2lv porb_level (
-	`ifdef LVS
-		.vpwr(vddio),
-		.vpb(vddio),
-		.lvpwr(vccd),
-		.vnb(vssio),
-		.vgnd(vssio),
-	`endif
+		.VPWR(vddio),
+		.VPB(vddio),
+		.LVPWR(vccd),
+		.VNB(vssio),
+		.VGND(vssio),
 		.A(porb_h),
 		.X(porb_l)
     );
@@ -578,6 +574,8 @@
     user_id_programming #(
 	.USER_PROJECT_ID(USER_PROJECT_ID)
     ) user_id_value (
+	.vdd1v8(vccd),
+	.vss(vssd),
 	.mask_rev(mask_rev)
     );
 
@@ -590,13 +588,11 @@
 
     // XRES (chip input pin reset) reset level converter
     sky130_fd_sc_hvl__lsbufhv2lv rstb_level (
-	`ifdef LVS
-		.vpwr(vddio),
-		.vpb(vddio),
-		.lvpwr(vdd1v8),
-		.vnb(vssio),
-		.vgnd(vssio),
-	`endif
+		.VPWR(vddio),
+		.VPB(vddio),
+		.LVPWR(vccd),
+		.VNB(vssio),
+		.VGND(vssio),
 		.A(rstb_h),
 		.X(rstb_l)
     );