Update README.md

verilog/dv/README.md

diff --git a/verilog/dv/README.md b/verilog/dv/README.md
index 2f4a77d..1c316a7 100644
--- a/verilog/dv/README.md
+++ b/verilog/dv/README.md
@@ -5,7 +5,7 @@
   * wb_utests: contains unit tests for the wishbone components residing at the management SoC private bus
 
 <pre>
-├── harness
+├── caravel
 │   ├── mgmt_soc
 │   ├── user_proj_example
 └── wb_utests