commit 08cd6eba30b5b59bbd33a808a9173203d7a7175b
author Matt Venn <matt@mattvenn.net> Mon Nov 16 12:01:14 2020 +0100
committer Matt Venn <matt@mattvenn.net> Mon Nov 16 12:01:14 2020 +0100
tree ed5d102ae14d7dca40e78ce0ae9a81ec0548cfd8
parent d4cc669e6b40d8f170c2674fe18ae0f43093f0c3

add default nettype none

verilog/rtl/digital_pll_controller.v

diff --git a/verilog/rtl/digital_pll_controller.v b/verilog/rtl/digital_pll_controller.v
index d4f7a4c..1437c93 100644
--- a/verilog/rtl/digital_pll_controller.v
+++ b/verilog/rtl/digital_pll_controller.v
@@ -1,3 +1,4 @@
+`default_nettype none
 // (True) digital PLL
 //
 // Output goes to a trimmable ring oscillator (see documentation).