Vast and substantial changes: Removed the old GPIO control with the new one
that implements a shift register around the perimeter of the chip, to control
most aspects of each GPIO pad locally to avoid excessive wiring. Added modules
for the metal-programmed user ID, two counter-timers, and a general-purpose SPI
master. The SPI master can be internally directly connected to the SPI slave,
so the processor can access the housekeeping SPI in the same way as an external
host. Most signals other than 1 GPIO pin and the SPI flash controller pins were
remapped to pads in the user area, where they are active on startup and until
they are programmed for user use from the management processor. There are
several known syntax issues that need to be fixed; this is a work in progress.
diff --git a/verilog/rtl/gpio_wb.v b/verilog/rtl/gpio_wb.v
index 9c55047..e4e92e9 100644
--- a/verilog/rtl/gpio_wb.v
+++ b/verilog/rtl/gpio_wb.v
@@ -18,11 +18,11 @@
output [31:0] wb_dat_o,
output wb_ack_o,
- input [1:0] gpio_in_pad,
- output [1:0] gpio,
- output [1:0] gpio_oeb,
- output [1:0] gpio_pu,
- output [1:0] gpio_pd
+ input gpio_in_pad,
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
);
wire resetn;
@@ -50,7 +50,7 @@
.iomem_addr(wb_adr_i),
.iomem_valid(valid),
- .iomem_wstrb(iomem_we),
+ .iomem_wstrb(iomem_we[0]),
.iomem_wdata(wb_dat_i),
.iomem_rdata(wb_dat_o),
.iomem_ready(ready),
@@ -73,25 +73,25 @@
input clk,
input resetn,
- input [1:0] gpio_in_pad,
+ input gpio_in_pad,
input [31:0] iomem_addr,
input iomem_valid,
- input [3:0] iomem_wstrb,
+ input iomem_wstrb,
input [31:0] iomem_wdata,
output reg [31:0] iomem_rdata,
output reg iomem_ready,
- output [1:0] gpio,
- output [1:0] gpio_oeb,
- output [1:0] gpio_pu,
- output [1:0] gpio_pd
+ output gpio,
+ output gpio_oeb,
+ output gpio_pu,
+ output gpio_pd
);
- reg [1:0] gpio; // GPIO output data
- reg [1:0] gpio_pu; // GPIO pull-up enable
- reg [1:0] gpio_pd; // GPIO pull-down enable
- reg [1:0] gpio_oeb; // GPIO output enable (sense negative)
+ reg gpio; // GPIO output data
+ reg gpio_pu; // GPIO pull-up enable
+ reg gpio_pd; // GPIO pull-down enable
+ reg gpio_oeb; // GPIO output enable (sense negative)
wire gpio_sel;
wire gpio_oeb_sel;
@@ -115,24 +115,20 @@
iomem_ready <= 1'b 1;
if (gpio_sel) begin
- iomem_rdata <= {14'd0, gpio, 14'd0, gpio_in_pad};
-
- if (iomem_wstrb[0]) gpio[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {30'd0, gpio, gpio_in_pad};
+ if (iomem_wstrb) gpio <= iomem_wdata[0];
end else if (gpio_oeb_sel) begin
- iomem_rdata <= {30'd0, gpio_oeb};
-
- if (iomem_wstrb[0]) gpio_oeb[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_oeb};
+ if (iomem_wstrb) gpio_oeb <= iomem_wdata[0];
end else if (gpio_pu_sel) begin
- iomem_rdata <= {30'd0, gpio_pu};
-
- if (iomem_wstrb[0]) gpio_pu[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_pu};
+ if (iomem_wstrb) gpio_pu <= iomem_wdata[0];
end else if (gpio_pd_sel) begin
- iomem_rdata <= {30'd0, gpio_pd};
-
- if (iomem_wstrb[0]) gpio_pd[ 1: 0] <= iomem_wdata[ 1: 0];
+ iomem_rdata <= {31'd0, gpio_pd};
+ if (iomem_wstrb) gpio_pd <= iomem_wdata[0];
end
