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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-017 / 99dbc249f8d9b17242220a367a68379643e3ada7
commit99dbc249f8d9b17242220a367a68379643e3ada7[log] [tgz]
authoragorararmard <aagouhar@efabless.com>Mon Nov 23 19:56:38 2020 +0200
committeragorararmard <aagouhar@efabless.com>Mon Nov 23 19:56:38 2020 +0200
treeb208e352b29cebf58c0a64e93518ba2c64abb74d
parentbc03551d8505ed018aad9cfbc77661ea6cfd8260 [diff]
a basic CI setup using the precheck
3 files changed
tree: b208e352b29cebf58c0a64e93518ba2c64abb74d
  1. .travisCI/
  2. def/
  3. doc/
  4. gds/
  5. lef/
  6. macros/
  7. mag/
  8. ngspice/
  9. openlane/
  10. scripts/
  11. spi/
  12. verilog/
  13. .travis.yml
  14. info.yaml
  15. LICENSE
  16. Makefile
  17. README.md
README.md

CIIC Harness

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware that can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC can be found here

Mega Project Area

This is the user space. It has limited silicon area (TBD, about 3.1mm x 3.8mm) as well as a fixed number of I/O pads (37) and power pads (10). See the Caravel premliminary datasheet for details. The repository contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.