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foss-eda-tools
/
third_party
/
shuttle
/
sky130
/
mpw-001
/
slot-017
/
975b34430c1d6c47ab714707f552da9794b91718
commit
975b34430c1d6c47ab714707f552da9794b91718
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log
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author
Ganesh Gore <goreganesh007@gmail.com>
Sun Dec 20 19:23:09 2020 -0700
committer
Ganesh Gore <goreganesh007@gmail.com>
Sun Dec 20 19:23:09 2020 -0700
tree
654ac32293fc8d158118593c7b37ced0456165f7
parent
77579f5e523e285af314d72e5ad3eeefd1b4285e
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[Localrun03] Added chip art + drc clean
checks/KlayoutMerge.log
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checks/caravel.magic.drc.mag
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checks/compare_caravel.txt
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checks/full_log.log
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checks/magic_drc.log
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checks/magic_extract.log
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checks/magic_merge_user_project_wrapper.log
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checks/manifest_check.mag.log
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checks/spdx_compliance_report.log
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gds/caravel.gds.gz
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gds/user_project_wrapper.gds.gz
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source_commit_hash.txt
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verilog/gl/caravel_sofa_hd_top.v
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13 files changed
tree: 654ac32293fc8d158118593c7b37ced0456165f7
checks/
def/
doc/
gds/
lef/
macros/
mag/
maglef/
ngspice/
OpenFPGA_task/
openlane/
qflow/
scripts/
spi/
utils/
verilog/
info.yaml
LICENSE
Makefile
mpw-one-b.md
README.md
source_commit_hash.txt
README.md
Caravel-SOFA-HD
Highlights
Opensource 12x12 FPGA designed using OpenFPGA prototyping tool
Designed with Skywater130nm PDK with HD standard cell library
Base K4 architecture from VPR with 40 vertical and horizontal channels
No adders (carry-chain) or flipflop reset pins
Designed using commercial PnR tool
Contribution
NOTE
This repository is created for The eFabless Open MPW shuttle program submission
The repository is auto-updated. For any commits issues and feature requests, please check
Skywater-OpenFPGA
Caravel design and CIIC Harness
For caravel related updated refer
efabless/caravel
