commit f8e6154eaeecd6d6edcfa19cda6a64cdd2f2db5d
author R. Timothy Edwards <tim@opencircuitdesign.com> Tue Nov 03 12:45:24 2020 -0500
committer GitHub <noreply@github.com> Tue Nov 03 12:45:24 2020 -0500
tree 77d6790bbcc4227a27f17ba1ab6271af650886f6
parent 263b8919e4acef39112d48fee944339edea0e3e7
parent 6bedda9543b474463eec0923966f1ff6cd2af56d

Merge pull request #29 from Manarabdelaty/param_adr

Added localparam for calculating mem address bits

verilog/rtl/mem_wb.v

diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index 607c684..3a16147 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -13,6 +13,9 @@
     output [31:0] wb_dat_o
     
 );
+
+    localparam ADR_WIDTH = $clog2(`MEM_WORDS);
+
     wire valid;
     wire ram_wen;
     wire [3:0] wen; // write enable
@@ -44,13 +47,16 @@
 
     soc_mem
 `ifndef USE_OPENRAM
-    #(.WORDS(`MEM_WORDS))
+    #(
+        .WORDS(`MEM_WORDS),
+        .ADR_WIDTH(ADR_WIDTH)
+    )
 `endif
      mem (
         .clk(wb_clk_i),
         .ena(valid),
         .wen(wen),
-        .addr(wb_adr_i[9:2]),
+        .addr(wb_adr_i[ADR_WIDTH+1:2]),
         .wdata(wb_dat_i),
         .rdata(wb_dat_o)
     );
@@ -60,14 +66,15 @@
 module soc_mem 
 `ifndef USE_OPENRAM
 #(
-    parameter integer WORDS = 256
+    parameter integer WORDS = 256,
+    parameter ADR_WIDTH = 8
 )
 `endif
  ( 
     input clk,
     input ena,
     input [3:0] wen,
-    input [7:0] addr,
+    input [ADR_WIDTH-1:0] addr,
     input [31:0] wdata,
     output[31:0] rdata
 );