Removed storage area from mgmt_core
- commented USE_OPENRAM in defines.v to use 1kb of synthesized memory
diff --git a/verilog/dv/caravel/sections.lds b/verilog/dv/caravel/sections.lds
index 0e80064..8da9aae 100644
--- a/verilog/dv/caravel/sections.lds
+++ b/verilog/dv/caravel/sections.lds
@@ -1,6 +1,6 @@
MEMORY {
FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x400000 /* 4MB */
- RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x1400 /* 1280 words (5 KB) */
+ RAM(xrw) : ORIGIN = 0x00000000, LENGTH = 0x0400 /* 256 words (1 KB) */
}
SECTIONS {
diff --git a/verilog/rtl/defines.v b/verilog/rtl/defines.v
index 5cc6d03..e2f457a 100644
--- a/verilog/rtl/defines.v
+++ b/verilog/rtl/defines.v
@@ -4,8 +4,7 @@
`define MPRJ_PWR_PADS 4 /* vdda1, vccd1, vdda2, vccd2 */
// Size of soc_mem_synth
-`define MEM_SYNTH_WORDS 1024
// Type and size of soc_mem
-`define USE_OPENRAM
+// `define USE_OPENRAM
`define MEM_WORDS 256
diff --git a/verilog/rtl/mem_synth_wb.v b/verilog/rtl/mem_synth_wb.v
deleted file mode 100644
index c4a1cc4..0000000
--- a/verilog/rtl/mem_synth_wb.v
+++ /dev/null
@@ -1,71 +0,0 @@
-module mem_synth_wb (
- input wb_clk_i,
- input wb_rst_i,
-
- input [31:0] wb_adr_i,
- input [31:0] wb_dat_i,
- input [3:0] wb_sel_i,
- input wb_we_i,
- input wb_cyc_i,
- input wb_stb_i,
-
- output wb_ack_o,
- output [31:0] wb_dat_o
-);
-
- wire valid;
- wire ram_wen;
- wire [3:0] wen; // write enable
-
- assign valid = wb_cyc_i & wb_stb_i;
- assign ram_wen = wb_we_i && valid;
-
- assign wen = wb_sel_i & {4{ram_wen}} ;
-
- reg wb_ack_read;
- reg wb_ack_o;
-
- always @(posedge wb_clk_i) begin
- if (wb_rst_i == 1'b 1) begin
- wb_ack_read <= 1'b0;
- wb_ack_o <= 1'b0;
- end else begin
- wb_ack_o <= wb_we_i? (valid & !wb_ack_o): wb_ack_read;
- wb_ack_read <= (valid & !wb_ack_o) & !wb_ack_read;
- end
- end
-
- soc_mem_synth mem (
- .clk(wb_clk_i),
- .ena(valid),
- .wen(wen),
- .addr(wb_adr_i[12:2]),
- .wdata(wb_dat_i),
- .rdata(wb_dat_o)
- );
-
-endmodule
-
-module soc_mem_synth (
- input clk,
- input ena,
- input [3:0] wen,
- input [10:0] addr,
- input [31:0] wdata,
- output[31:0] rdata
-);
-
- reg [31:0] rdata;
- reg [31:0] mem [0:`MEM_SYNTH_WORDS-1];
-
- always @(posedge clk) begin
- if (ena == 1'b1) begin
- rdata <= mem[addr];
- if (wen[0]) mem[addr][ 7: 0] <= wdata[ 7: 0];
- if (wen[1]) mem[addr][15: 8] <= wdata[15: 8];
- if (wen[2]) mem[addr][23:16] <= wdata[23:16];
- if (wen[3]) mem[addr][31:24] <= wdata[31:24];
- end
- end
-
-endmodule
diff --git a/verilog/rtl/mem_wb.v b/verilog/rtl/mem_wb.v
index f9cfd62..607c684 100644
--- a/verilog/rtl/mem_wb.v
+++ b/verilog/rtl/mem_wb.v
@@ -22,10 +22,6 @@
assign wen = wb_sel_i & {4{ram_wen}} ;
-`ifndef USE_OPENRAM
- assign wb_ack_o = valid;
-`else
-
/*
Ack Generation
- write transaction: asserted upon receiving adr_i & dat_i
@@ -46,8 +42,6 @@
end
end
-`endif
-
soc_mem
`ifndef USE_OPENRAM
#(.WORDS(`MEM_WORDS))
@@ -56,7 +50,7 @@
.clk(wb_clk_i),
.ena(valid),
.wen(wen),
- .addr(wb_adr_i[23:2]),
+ .addr(wb_adr_i[9:2]),
.wdata(wb_dat_i),
.rdata(wb_dat_o)
);
@@ -66,14 +60,14 @@
module soc_mem
`ifndef USE_OPENRAM
#(
- parameter integer WORDS = 8192
+ parameter integer WORDS = 256
)
`endif
(
input clk,
input ena,
input [3:0] wen,
- input [21:0] addr,
+ input [7:0] addr,
input [31:0] wdata,
output[31:0] rdata
);
@@ -107,4 +101,4 @@
`endif
-endmodule
+endmodule
\ No newline at end of file
diff --git a/verilog/rtl/mgmt_soc.v b/verilog/rtl/mgmt_soc.v
index 55d0d2d..1139f1d 100644
--- a/verilog/rtl/mgmt_soc.v
+++ b/verilog/rtl/mgmt_soc.v
@@ -42,7 +42,6 @@
`include "la_wb.v"
`include "mprj_ctrl.v"
`include "convert_gpio_sigs.v"
-`include "mem_synth_wb.v"
module mgmt_soc (
`ifdef LVS
@@ -141,13 +140,12 @@
output [31:0] mprj_dat_o
);
/* Memory reverted back to 256 words while memory has to be synthesized */
- parameter [31:0] STACKADDR = (4*(`MEM_WORDS + `MEM_SYNTH_WORDS)); // end of memory
+ parameter [31:0] STACKADDR = (4*(`MEM_WORDS)); // end of memory
parameter [31:0] PROGADDR_RESET = 32'h 1000_0000;
parameter [31:0] PROGADDR_IRQ = 32'h 0000_0000;
// Slaves Base Addresses
parameter RAM_BASE_ADR = 32'h 0000_0000;
- parameter RAM_SYNTH_BASE_ADR = 32'h 0100_0000;
parameter FLASH_BASE_ADR = 32'h 1000_0000;
parameter UART_BASE_ADR = 32'h 2000_0000;
parameter GPIO_BASE_ADR = 32'h 2100_0000;
@@ -203,7 +201,7 @@
// Wishbone Interconnect
localparam ADR_WIDTH = 32;
localparam DAT_WIDTH = 32;
- localparam NUM_SLAVES = 13;
+ localparam NUM_SLAVES = 12;
parameter [NUM_SLAVES*ADR_WIDTH-1: 0] ADR_MASK = {
{8'hFF, {ADR_WIDTH-8{1'b0}}},
@@ -217,7 +215,6 @@
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}},
- {8'hFF, {ADR_WIDTH-8{1'b0}}},
{8'hFF, {ADR_WIDTH-8{1'b0}}}
};
@@ -233,7 +230,6 @@
{GPIO_BASE_ADR},
{UART_BASE_ADR},
{FLASH_BASE_ADR},
- {RAM_SYNTH_BASE_ADR},
{RAM_BASE_ADR}
};
@@ -717,24 +713,6 @@
.wb_dat_o(mem_dat_o)
);
- // Wishbone Slave Synthesized RAM
- wire mem_synth_stb_i;
- wire mem_synth_ack_o;
- wire [31:0] mem_synth_dat_o;
-
- mem_synth_wb soc_mem_synth (
- .wb_clk_i(wb_clk_i),
- .wb_rst_i(wb_rst_i),
- .wb_adr_i(cpu_adr_o),
- .wb_dat_i(cpu_dat_o),
- .wb_sel_i(cpu_sel_o),
- .wb_we_i(cpu_we_o),
- .wb_cyc_i(cpu_cyc_o),
- .wb_stb_i(mem_synth_stb_i),
- .wb_ack_o(mem_synth_ack_o),
- .wb_dat_o(mem_synth_dat_o)
- );
-
// Wishbone intercon logic
wb_intercon #(
.AW(ADR_WIDTH),
@@ -754,17 +732,17 @@
mprj_stb_o, mprj_ctrl_stb_i, la_stb_i,
spi_master_stb_i, counter_timer1_stb_i, counter_timer0_stb_i,
gpio_stb_i, uart_stb_i,
- spimemio_flash_stb_i, mem_synth_stb_i, mem_stb_i }),
+ spimemio_flash_stb_i, mem_stb_i }),
.wbs_dat_i({ sys_dat_o, spimemio_cfg_dat_o,
mprj_dat_i, mprj_ctrl_dat_o, la_dat_o,
spi_master_dat_o, counter_timer1_dat_o, counter_timer0_dat_o,
gpio_dat_o, uart_dat_o,
- spimemio_flash_dat_o,mem_synth_dat_o, mem_dat_o }),
+ spimemio_flash_dat_o, mem_dat_o }),
.wbs_ack_i({ sys_ack_o, spimemio_cfg_ack_o,
mprj_ack_i, mprj_ctrl_ack_o, la_ack_o,
spi_master_ack_o, counter_timer1_ack_o, counter_timer0_ack_o,
gpio_ack_o, uart_ack_o,
- spimemio_flash_ack_o, mem_synth_ack_o, mem_ack_o })
+ spimemio_flash_ack_o, mem_ack_o })
);
endmodule
