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foss-eda-tools / third_party / shuttle / sky130 / mpw-001 / slot-016 / ca2f318bb428801e0739cc341d80def2d8c70559
commitca2f318bb428801e0739cc341d80def2d8c70559[log] [tgz]
authorTim Edwards <tim@opencircuitdesign.com>Tue Oct 06 10:05:11 2020 -0400
committerTim Edwards <tim@opencircuitdesign.com>Tue Oct 06 10:05:11 2020 -0400
treee3893a840869be501ecd824b809615bae1bc67da
parentf51dd08a1f4716df0cca0a0ebe28f99544cc611c [diff]
Various corrections to simplify the user project I/O wiring
connections into the management area.  Corrected testbenches
for hkspi, mem, uart, perf, and gpio.
17 files changed
tree: e3893a840869be501ecd824b809615bae1bc67da
  1. doc/
  2. verilog/
  3. README.md
README.md

CIIC Harness (Phase 1)

A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.

Managment SoC

The managment SoC runs firmware taht can be used to:

  • Configure Mega Project I/O pads
  • Observe and control Mega Project signals (through on-chip logic analyzer probes)
  • Control the Mega Project power supply

The memory map of the management SoC is given below

Mega Project Area

This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.

The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided:

  1. Configure the Mega Project I/O pads as o/p. Observe the counter value in the testbench: IO_Ports Test.
  2. Configure the Mega Project I/O pads as o/p. Use the Chip LA to load the counter and observe the o/p till it reaches 500: LA_Test1.
  3. Configure the Mega Project I/O pads as o/p. Use the Chip LA to control the clock source and reset signals and observe the counter value for five clock cylcles: LA_Test2.