| commit | 04ba17f7ad1e0fd5ea56b89a6bb64d61d6fe1923 | [log] [tgz] |
|---|---|---|
| author | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 02 22:27:50 2020 -0400 |
| committer | Tim Edwards <tim@opencircuitdesign.com> | Fri Oct 02 22:27:50 2020 -0400 |
| tree | 141f8da9f8b6ec4a73e8efd2416de0967b7fa5aa | |
| parent | 49e2c187475c37294d48459aac6cb1e3d96d676a [diff] |
Vast and substantial changes: Removed the old GPIO control with the new one that implements a shift register around the perimeter of the chip, to control most aspects of each GPIO pad locally to avoid excessive wiring. Added modules for the metal-programmed user ID, two counter-timers, and a general-purpose SPI master. The SPI master can be internally directly connected to the SPI slave, so the processor can access the housekeeping SPI in the same way as an external host. Most signals other than 1 GPIO pin and the SPI flash controller pins were remapped to pads in the user area, where they are active on startup and until they are programmed for user use from the management processor. There are several known syntax issues that need to be fixed; this is a work in progress.
A template SoC for Google SKY130 free shuttles. It is still WIP. The current SoC architecture is given below.
The managment SoC runs firmware taht can be used to:
The memory map of the management SoC is given below
This is the user space. It has limitted silicon area (???) as well as a fixed number of I/O pads (???). The repoo contains a sample mega project that contains a binary 32-bit up counter.
The firmware running on the Management Area SoC, configures the I/O pads used by the counter and uses the logic probes to observe/control the counter. Three firmware examples are provided: